• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.895-898
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• 2005

This paper describes a design of LNS-based divider and square-root circuits which are key arithmetic units in graphic processor and digital signal processor. To achive area-efficient and low-power that is an essential consideration for mobile environment, a fixed-point format of 16.16 is adopted instead of conventional floating-point format. The designed divider and square-root units consist of binary-to-logarithm converter, subtractor, logarithm-to-binary converter. The binary to logarithm converter is designed using combinational logic based on six regions approximation method. As a result, gate count reduction is obtained when compared with conventional lookup approack. The designed units is 3,130 gate count and 1,280 gate count. To minimize average percent error 3.8% and 4.2%. error compensation method is employed.

• Proceedings of the Korea Contents Association Conference
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• 2009.05a
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• pp.737-742
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• 2009

As increasing emphasis is being placed on user experience design, the RIA technology is widely deployed for user interface and software operation on embedded devices including cell phones and TVs. In particular, RIA-based IPTV enables creation of various interactive contents via sophisticated animation and various input devices. This paper proposes a service framework for emotional contents on broadcast and communication-converged IPTV systems. We design a programming interface extension for IPTV-based flash contents and develop a prototype of flash runtime with the extended programming support. Since the proposed runtime was carefully designed to fully utilize the built-in graphic acceleration hardware in media processor, it supports high resolution graphic animation in resource-constrained IPTV environments.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.226-231
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• 1991

A graphic control language using function block diagram approach is designed and implemented, applicable to real-time control for continuous process automation system. The procedure implementing the control language is composed of three parts, editor, compiler, and executer. The editor generates the control algorithm file, which contains function block information in the text form, by menu-driven method on the color graphic screen. The compiler translates the contents of the control algorithm file to machine codes and their related data. Then, the executer generates a task that makes the machine codes executed at every sampling period in the target processor. The validity of the concept in its design and implementaion is assured by on-line simulation in the multi-function controller designed for continuous process automation.

• Computational Structural Engineering
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• v.2 no.4
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• pp.69-77
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• 1989

Until recently post-processing of finite element model has been heavily relied on expensive graphic peripheral devices. With the aid of inexpensive microcomputers, very economical post-processor graphics program called MICRO-POST has been developed. Model geometry or results of analysis for the unlimited meshes can be easily presented in a number of low-cost graphic devices. The paper presents the procedure obtaining the device-independent graphics, and the structure and functions of the program. It also describes efficient I/O scheme to overcome the memory limitation, and dialogue-type input technique to control the plot operation in an interactive manner. Through the post processing examples for the general purpose finite element programs, it demonstrates the usefulness of the program.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2691-2697
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• 2010

Shader instructions and Compiler are designed for supporting 3D graphic shader 3.0 API. Variable-length instructions are proposed to reduce the size of hardware of graphic processor in SIMD structure by shortening the length of instructions. The designed shader compiler supports variable and two phased structured instructions, and can be programmable at ESSL level. Conformance Test proposed by Khronos group is accomplished to verify the design result of instructions and complier. The test result shows overall average 37% performance improvement at the 16 functions of basic GL shader.

• Proceedings of the Korean Society of Computer Information Conference
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• 2012.07a
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• pp.9-11
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• 2012

프로세서 설계 기술의 발달로 인해 그래픽 프로세서 또한 기술적으로 크게 발전하였다. 그래픽 프로세서는 단순한 그래픽 표현장치에서 대용량의 데이터를 병렬로 처리하는 고성능 장치로 변화하고 있다. 뿐만 아니라 그래픽 프로세서는 대용량의 데이터처리가 가능한 병렬 프로세서로 특화되어 있기 때문에 이를 활용하여 CPU의 작업을 보조하며 빠른 연산 수행을 가능하게 한다. 이로 인해, 최신의 고성능 시스템 설계에서 그래픽 프로세서는 매우 중요한 역할을 한다. 그래픽 프로세서를 활용하는 고성능의 시스템을 설계하기 위해서는 발열과 소비 전력을 고려해야 한다. 본 논문에서는 그래픽 프로세서의 온도를 제어하는 냉각팬의 세기를 조절하여 그에 따른 온도와 소비 전력을 분석한다. 실험 결과 냉각팬 세기가 낮은 경우 그래픽 프로세서의 온도는 $100^{\circ}C$까지 급격히 상승한다. 냉각팬 세기가 높은 경우 그래픽 프로세서의 온도는 천천히 증가하여 일정 온도에 수렴함을 알 수 있다. 또한, 그래픽 프로세서의 소비 전력은 작업량을 할당하지 않았을 때보다 최대작업량을 할당하였을 때 냉각팬 세기에 따른 소비전력 차이가 큼을 알 수 있다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.281-284
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• 2008

Recently, Khronos institude OpenGL ES 2.0 API for support Shader 3.0 model that can possible variable graphic processing. For this reason, the mobile device have need of supporting processor for a shader 3.0 model. We should extend instruction's length to support OpenGL ES 2.0 API, so we need more memory size. In this paper, we propose a new instruction form that adopted variable length and unit instruction architecture. This proposed instruction architecture that support to Shader 3.0 model has consist of 32bit unit instructions up to 4 which can be combined for embellishing each other. Therefore, it can execute flexible instruction combination and reduce waste of instruction fields.

• Journal of Institute of Control, Robotics and Systems
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• v.11 no.1
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• pp.84-91
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• 2005

In this paper, we describe the real-time parallel processing simulator developed for the use of performance analysis of rolling missiles. The real-time parallel processing simulator developed here consists of seeker emulator generating infrared image signal on aircraft, real-time computer, host computer, system unit, and actual equipments such as auto-pilot processor and seeker processor. Software is developed from mathematic models, 6 degree-of-freedom module, aerodynamic module which are resided in real-time computer, and graphic user interface program resided in host computer. The real-time computer consists of six TIC-40 processors connected in parallel. The seeker emulator is designed by using analog circuits coupled with mechanical equipments. The system unit provides interface function to match impedance between the components and processes very small electrical signals. Also real launch unit of missiles is interfaced to simulator through system unit. In order to apply the real-time parallel processing simulator to performance analysis equipment of rolling missiles it is essential to perform the performance verification test of simulator.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.5
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• pp.97-103
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• 2010

There are many algorithms for 2D to 3D graphic conversion technology which have the high complexity and large scale of iterative computation. So in this paper propose parallel algorithm and high speed graphics accelerator architecture using Park's MAMS(Multiple Access Memory System) for Phong Shading, one of many 3D algorithms. The Proposed SIMD processor architecture is simulated by HDL and simulated and got 30 times faster result. It means any kinds of 3D algorithm can make parallel algorithm and accelerated by SIMD processor with Park's MAMS for real time processing.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.2
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• pp.239-246
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• 2015

Video based object detection is basic technology of implementing smart CCTV system. Various features and algorithms are developed to detect object, however computations of them increase with the performance. In this paper, performances of object detection algorithms with GPU and CPU are compared. Adaboost and SVM algorithm which are widely used to detect pedestrian detection are implemented with CPU and GPU, and speeds of detection processing are compared for the same video. As results of frame rate comparison of Adaboost and SVM algorithm, it is shown that the frame rate with GPU is faster than CPU.