• The Transactions of the Korea Information Processing Society
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• v.6 no.4
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• pp.877-890
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• 1999

In this paper, a multimedia mail including video, sound, graphic data has been proposed as the next generation mail of the text based mail. In order to develop the multimedia mail, the most outstanding problem is the fact that the multimedia data are too huge to send them to the receiving end directly. The fact of big data may cause many problems in both transferring and storing the data of the multimedia mail. Our main idea is to separate between a control program for the multimedia presentation and multimedia data. Since the size of a control program is as small as a plain text mail, it has no problem to send it attached to the internet mail to the receiver directly. Instead, the big multimedia data themselves may remain on the sender's computer or be sent to a designated server so that the data may be transferred to the receiver only when the receiver activates the play of the multimedia mail. In this scheme, our research focus is paced on the buffer management and the thread scheduling for the real time play of the multimedia mail on internet. Another problem is to provide an easy way of editing a multimedia presentation for an ordinary people having no programming knowledge. For the purposed, VIP(Visual Interface Player) has been used and the results or multimedia mail implemented on LAN has been described.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.86-94
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• 2012

In this paper we propose a hardware architecture of high-speed CGH (computer generated hologram) generation processor, which particularly reduces the number of memory access times to avoid the bottle-neck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation rather than light source-by-source calculation. The second is parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last one is a fully pipelined calculation scheme and exactly structured timing scheduling by adjusting the hardware. The proposed hardware is structured to calculate a row of a CGH in parallel and each hologram pixel in a row is calculated independently. It consists of input interface, initial parameter calculator, hologram pixel calculators, line buffer, and memory controller. The implemented hardware to calculate a row of a $1,920{\times}1,080$ CGH in parallel uses 168,960 LUTs, 153,944 registers, and 19,212 DSP blocks in an Altera FPGA environment. It can stably operate at 198MHz. Because of the three schemes, the time to access the external memory is reduced to about 1/20,000 of the previous ones at the same calculation speed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.