• Journal of the Korean Society of Industry Convergence
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• v.26 no.5
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• pp.945-952
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• 2023

In this study, the sand casting process was applied to design the gating system and perform casting simulation in order to domestically produce the submarine mast cover. Based on simulation results, casting experiments were conducted to produce a soundness prototype. The design concept of the mast cover's gating system was based on the design of bell casting. By arranging eight tower-type gates in a circle at 45° intervals, the flow of melt flowing into each gate was uniform and did not mix with each other, and the velocity of melt was also uniform. The mast cover made of Ni-Al-Bronze alloy has no unfilled parts. However, small porosities and flow marks occurred on the surface in several places. Yield strength and ultimate tensile strength are 279.3 MPa and 675.7 MPa, respectively, and elongation is 21.2%.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.865-868
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• 2005

This paper presents a Clock-gating technique that reduces power dissipation of the sequential circuits in the system. The Master Clock of a Clock-gating technique is formed by a quaternary variable. It uses the covering relationship between the triggering transition of the clock and the active cycles of various flip-flops to generate a slave clock for each flip-flop in the circuit. At current RTL designs flip-flop is acted by Master clock's triggering but the Slave Clock of Clock-gating technique doesn't occur trigger when external input conditions have not matched with a condition of logic table. We have applied our clocking technique to UART controller of 8bit microprocess

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.56-63
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• 2015

Not only performance analysis but also power analysis at early design stages is important in designing a system-on-chip. We propose a power modeling based on clock gating enable signals that enables accurate power analysis at a high-level. Power state is defined as combinations of the values of the clock gating enable signals and we can extract the clock gating enable signals to generate the power model automatically. Experimental results show that the average power accuracy is about 96% and the speed gain of power analysis at the high-level power is about 280 times compared to that at the gate-level.

• International Journal of Control, Automation, and Systems
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• v.2 no.1
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• pp.23-38
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• 2004

We proposed the infinity control principle to evaluate the Biological function. The H infinity control was applied to the Sodium (Na) ion selective gating channel on the excitable cellular membrane of the neural system. The channel opening, closing and inactivation processes were expressed by movements of three gates and one inactivation blocking particle in the channel pore. The rate constants of the channel state transition were set to be voltage dependent. The temporal changes in amounts per unit membrane area of the channel states were expressed by means of eight differential equations. The biochemical mimetic used to complete the Na ion selective channel was regarded as noise. The control inputs for ejecting the blocking particle with plugging in the channel pore were set for the active transition from inactivated states to a closed or open state. By applying the H infinity control, we computed temporal changes in the channel states, observers, control inputs and the worst case noises. The present paper will be available for evaluating the noise filtering function of the biological signal transmission system.

• Progress in Medical Physics
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• v.26 no.2
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• pp.87-92
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• 2015

The gated RapidArc may produce a dosimetric error due to the stop-and-go motion of heavy gantry which can misalign the gantry restart position and reduce the accuracy of important factors in RapidArc delivery such as MLC movement and gantry speed. In this study, the effect of stop-and-go motion in gated RapidArc was analyzed with varying gating window time, which determines the total number of stop-and-go motions. Total 10 RapidArc plans for treatment of liver cancer were prepared. The RPM gating system and the moving phantom were used to set up the accurate gating window time. Two different delivery quality assurance (DQA) plans were created for each RapidArc plan. One is the portal dosimetry plan and the other is MapCHECK2 plan. The respiratory cycle was set to 4 sec and DQA plans were delivered with three different gating conditions: no gating, 1-sec gating window, and 2-sec gating window. The error between calculated dose and measured dose was evaluated based on the pass rate calculated using the gamma evaluation method with 3%/3 mm criteria. The average pass rates in the portal dosimetry plans were $98.72{\pm}0.82%$, $94.91{\pm}1.64%$, and $98.23{\pm}0.97%$ for no gating, 1-sec gating, and 2-sec gating, respectively. The average pass rates in MapCHECK2 plans were $97.80{\pm}0.91%$, $95.38{\pm}1.31%$, and $97.50{\pm}0.96%$ for no gating, 1-sec gating, and 2-sec gating, respectively. We verified that the dosimetric accuracy of gated RapidArc increases as gating window time increases and efforts should be made to increase gating window time during the RapidArc treatment process.

• Proceedings of the Korean Society of Medical Physics Conference
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• 2006.08a
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• pp.82-82
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• 2006

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.1
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• pp.16-24
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• 2011

Automotive Radar Systems are currently under development for various applications to increase accuracy and reliability. The target tracking is most important in single or multiple target environments for accuracy. The tracking algorithm provides smoothed and predicted data for target position and velocity(Doppler). To this end, the fixed gain filter(${\alpha}{\beta}$ filter, ${\alpha}{\beta}{\gamma}$ filter) and dynamic filter(Kalman filter, Singer-Kalman filter, etc) are commonly used. Gating is used to decide whether an observation is assigned to an existing track or new track. Gating algorithms are normally based on computing a statistical error distance between an observation and prediction. The data association takes the observation-to-track pairings that satisfied gating and determines which observation-to-track assignment will actually be made. For data association, NNPDA(Nearest Neighbor Probabilistic Data Association) algorithm is proposed. In this paper, we designed a target tracking system developed for an Automotive Radar System. We show the experimental results of the 77GHz FMCW radar sensor on the roads. Four tracking algorithms(${\alpha}{\beta}$ filter, ${\alpha}{\beta}{\gamma}$ filter, 2nd order Kalman filter, Singer-Kalman filter) have been compared and analyzed to evaluate the performance in test scenario.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.1-7
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• 2009

This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

• Journal of Sensor Science and Technology
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• v.26 no.3
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• pp.209-213
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• 2017

The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of high area overhead and high power consumption. This paper proposes a new NCL gate based on power gating structure. The proposed $4{\times}4$ NCL multiplier based on power gating structure is compared to the conventional NCL $4{\times}4$ multiplier and MTNCL(Multi-Threshold NCL) $4{\times}4$ multiplier in terms of speed, power consumption, energy and size using PTM 45 nm technology.

• Journal of Korea Foundry Society
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• v.28 no.4
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• pp.190-194
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• 2008

Thin-walled die casting of aluminum notebook computer housing with less than 1mm thickness was investigated by using computational solidification simulation and actual casting experiment. Three different types of gate design, finger, tangential and split type, were used and the results showed that sound thin-walled die casting was possible with tangential and split type gating design because those gates allowed aluminum melt flowed into the thin-wall cavity uniformly and split type gating system was preferable gating design than tangential type at the point of view of soundness of casting and distortion generated after solidification. Also, solidification simulation agreed well with the actual die-casting and the casting showed no casting defect and distortion.