• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제22권5호
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• pp.386-389
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• 2009

The electrical characteristics and annealing effects of tunneling dielectrics stacked with $SiO_2$ and $Si_{3}N_{4}$ were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_{3}N_{4}/SiO_2/Si_{3}N_{4}$ (NON), $SiO_2/Si_{3}N_{4}/SiO_2$ (ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS (metal-oxide-semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field. Furthermore, the increased tunneling current through engineered tunneling barriers related to high speed operation can be achieved by annealing processes.

• Journal of the Korean Institute of Telematics and Electronics
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• 제27권11호
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• pp.135-143
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• 1990

A new over-the-cell routing system is proposed in this paper. The proposed system efficiently reduces not only the channel density but also the routing density in cell region. Generally, the over-the-cell system consists of three phases. Namely, over-the-cell routing, terminal selection and channel routing. In this paper, to select the nets to be routed over the cells, weights are assigned on the intersection graph considering both the channel density and the intersection relations among other nets. When selected nets are blocked by feedthroughs or metal layers for internal logic, they are routed by maze algorithm. Also, in order to reduce channel density, the terminals to be routed in a channel are selected using the minimum weight spanning tree. Channel routing is carried out with a channel router of HAN-LACAD_G. The effectiveness of the over-the-cell routing system is shown by the experiments with benchmark data and its application to the gate array layout system.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.121-129
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• 2011

It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, the cell size of the NAND Flash memory has been scaled down by merely 50% and has been doubling density each per year. [1] However, side effects have arisen the cell distribution and reliability characteristics related to coupling interference, channel disturbance, floating gate electron retention, write-erase cycling owing to shrinking around 20nm technology. Also, FLASH controller to manage shrink effect leads to speed and current issues. In this paper, It will be introduced to solve cycling, retention and fail bit problems of sub-deep micron shrink such as Virtual negative read used in moving read, randomization. The characteristics of retention, cycling and program performance have 3 K per 1 year and 12.7 MB/s respectively. And device size is 179.32 $mm^2$ (16.79 mm ${\times}$ 10.68 mm) in 3 metal 26 nm CMOS.

• Korean Journal of Materials Research
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• 제18권3호
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• pp.148-152
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• 2008

A new cost-effective atomic layer deposition (ALD) technique, known as Proximity-Scan ALD (PS-ALD) was developed and its benefits were demonstrated by depositing $Al_2O_3$ and $HfO_2$ thin films using TMA and TEMAHf, respectively, as precursors. The system is consisted of two separate injectors for precursors and reactants that are placed near a heated substrate at a proximity of less than 1 cm. The bell-shaped injector chamber separated but close to the substrate forms a local chamber, maintaining higher pressure compared to the rest of chamber. Therefore, a system configuration with a rotating substrate gives the typical sequential deposition process of ALD under a continuous source flow without the need for gas switching. As the pressure required for the deposition is achieved in a small local volume, the need for an expensive metal organic (MO) source is reduced by a factor of approximately 100 concerning the volume ratio of local to total chambers. Under an optimized deposition condition, the deposition rates of $Al_2O_3$ and $HfO_2$ were $1.3\;{\AA}/cycle$ and $0.75\;{\AA}/cycle$, respectively, with dielectric constants of 9.4 and 23. A relatively short cycle time ($5{\sim}10\;sec$) due to the lack of the time-consuming "purging and pumping" process and the capability of multi-wafer processing of the proposed technology offer a very high through-put in addition to a lower cost.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.74-77
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• 2004

[ $HfO_2$ ] dielectric layers were grown on the p-type Si(100) substrate by metalorganic molecular beam epitaxy(MOMBE). Hafnium $t-butoxide[Hf(O{\cdot}t-C_4H_9)_4]$ was used as a Hf precursor and Argon gas was used as a carrier gas. The thickness of the layers was measured by scanning electron microscopy (SEM) and high-resolution transmission electron measurement(HR-TEM). The properties of the $HfO_2$ layers were evaluated by X-ray diffraction(XRD), high frequency capacitance-voltage measurement(HF C-V), current-voltage measurement(I-V), and atomic force measurement(AFM). HF C-V measurements have shown that $HfO_2$ layer grown by MOMBE has a high dielectric constant(k=19-21). The properties of $HfO_2$ films are affected by various process variables such as substrate temperature, bubbler temperature, Ar, and $O_2$ gas flows. In this paper, we examined the relationship between the $O_2/Ar$ gas ratio and the electrical properties of $HfO_2$.

• Journal of Digital Convergence
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• 제16권12호
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• pp.309-315
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• 2018

In this paper, propose an efficient arc detection and control method to achieve fast machining speed, improved precision and surface roughness in discharge machining, especially for carbide and hard material processing and metal processing using discharge phenomenon as energy. A single discharge waveform is divided into three sections of Td (Time-Delay), Ton (Time-on) and Toff (Time-off) and the gate control timing is simulated using the HDL language. In this paper, we analyze the effect of the gap between the electrode and the workpiece on the machining results by determining the operation of the servo mechanism by sampling the Td section through the comparator circuit. As a result of the analysis, the Td section of the formed waveform was more precisely sampled at a high speed and the results were improved when applied to the gap control between the electrode and the workpiece.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제37권1호
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• pp.101-105
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• 2024

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the D_it.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제27권9C호
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• pp.861-870
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• 2002

In this paper, with targeting on the drawback of RSA of operation speed, a new 1024-bit RSA cryptosystem has been proposed and implemented in hardware to increase the operational speed and perform the variable-length encryption. The proposed cryptosystem mainly consists of the modular exponentiation part and the modular multiplication part. For the modular exponentiation, the RL-binary method, which performs squaring and modular multiplying in parallel, was improved, and then applied. And 4-stage CSA structure and radix-4 booth algorithm were applied to enhance the variable-length operation and reduce the number of partial product in modular multiplication arithmetic. The proposed RSA cryptosystem which can calculate at most 1024 bits at a tittle was mapped into the integrated circuit using the Hynix Phantom Cell Library for Hynix 0.35㎛ 2-Poly 4-Metal CMOS process. Also, the result of software implementation, which had been programmed prior to the hardware research, has been used to verify the operation of the hardware system. The size of the result from the hardware implementation was about 190k gate count and the operational clock frequency was 150㎒. By considering a variable-length of modulus number, the baud rate of the proposed scheme is one and half times faster than the previous works. Therefore, the proposed high speed variable-length RSA cryptosystem should be able to be used in various information security system which requires high speed operation.

• Journal of the Korea Academia-Industrial cooperation Society
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• 제21권6호
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• pp.482-489
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• 2020

This study conducted a prototype development and evaluation by performing die-casting mold design, mold manufacturing, and injection condition optimization based on flow and solidification analysis to meet the needs of the coupling parts produced by die casting. Through flow analysis, the injection conditions suitable for 100% filling in the cavity were found to be a molten metal temperature of 670 ℃, injection speed of 1.164 m/s, and filling pressure of 6.324~18.77 MPa. In addition, solidification close to 100 % occurred in all four cavities when the solidification rate was 69.47 %. A defect inspection on the surface and inside the product revealed defects, such as poor molding and pores. In addition, the dimensions of the injected product were within the target tolerance and showed good results. Through the feedback of the results of flow and solidification analysis, it was possible to optimize the mold design, and the injection optimization conditions were confirmed to be a total cycle time of approximately 6.5 seconds. Good quality carrier parts with an average surface hardness of approximately 45 mm from the gate measured at 97.48(Hv) could be produced.

• Proceedings of the Materials Research Society of Korea Conference
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• 한국재료학회 2009년도 추계학술발표대회
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• pp.24.1-24.1
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• 2009

Tantalum carbo-nitride($T_aC_xN_y$) films were deposited with chemical vapor deposition(CVD) using tert-butylimido tris-diethylamido tantalum (TBTDET, $^tBu-N=Ta-(NEt_2)_3$, $Et=C_2H_5$, $^tBu=C(CH_3)_3$) between $350^{\circ}C$ and $600^{\circ}C$ with argon as a carrier gas. Fourier transform infrared (FT-IR)spectroscopy was used to study the thermal decomposition behavior of TBTDET in the gas phase. When the temperature was increased, C-H and C-N bonding of TBTDET disappeared and the peaks of ethylene appeared above $450^{\circ}C$ in the gas phase. The growth rate and film density of $T_aC_xN_y$ film were in the range of 0.1nm/min to 1.30nm/min and of $8.92g/cm^3$ to $10.6g/cm^3$ depending on the deposition temperature. $T_aC_xN_y$ films deposited below $400^{\circ}C$ were amorphous and became polycrystal line above $500^{\circ}C$. It was confirmed that the $T_aC_xN_y$ film was a mixture of TaC, graphite, $Ta_3N_5$, TaN, and $Ta_2O_5$ phases and the oxide phase was formed from the post deposition oxygen uptake. With the increase of the deposition temperature, the TaN phase was increased over TaC and $Ta_3N_5$ and crystallinity, work function, conductivity and density of the film were increased. Also the oxygen uptake was decreased due to the increase of the film density. With the increase of the TaC phase in $T_aC_xN_y$ film, the work function was decreased to 4.25eV and with the increase of the TaN phase in $T_aC_xN_y$ film,it was increased to 4.48eV.