• IEIE Transactions on Smart Processing and Computing
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• v.6 no.3
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• pp.210-219
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• 2017

This paper proposes a modified min-max algorithm (MMMA) for nonbinary quasi-cyclic low-density parity-check (NB-QC-LDPC) codes and an efficient parallel block-layered decoder architecture corresponding to the algorithm on a graphics processing unit (GPU) platform. The algorithm removes multiplications over the Galois field (GF) in the merger step to reduce decoding latency without any performance loss. The decoding implementation on a GPU for NB-QC-LDPC codes achieves improvements in both flexibility and scalability. To perform the decoding on the GPU, data and memory structures suitable for parallel computing are designed. The implementation results for NB-QC-LDPC codes over GF(32) and GF(64) demonstrate that the parallel block-layered decoding on a GPU accelerates the decoding process to provide a faster decoding runtime, and obtains a higher coding gain under a low $10^{-10}$ bit error rate and low $10^{-7}$ frame error rate, compared to existing methods.

• Annual Conference on Human and Language Technology
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• 2012.10a
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• pp.119-120
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• 2012

GPU를 이용한 병렬 알고리즘은 어떤 메모리를 사용하는지에 따라 시스템의 전체적인 성능이 달라진다. 본 논문은 GPU 환경에서 실행되는 CUDA 프레임워크에서 병렬처리를 이용하여 문서 분류 시스템의 속도를 향상시키고자 할 때 메모리 로딩 시간이 전체적인 시스템의 성능에 미치는 영항을 연구하였다. 기존의 CPU 환경에서 구현했을 때와 비교하여 어느 정도의 성능 향상이 있었는지 실험하였으며 이전 연구에서 고려하지 않았던 메모리를 읽는데 걸리는 시간을 고려하여 현실적인 실행 시간을 비교하였다. 실험 결과에 의하면 CPU 에서 구현했을 때의 연산 속도보다 GPU의 텍스쳐 메모리를 사용하여 구현하였을 때 문서분류 성능이 향상되는 효과가 있음을 알 수 있었다.

• 한국HCI학회:학술대회논문집
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• 2009.02a
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• pp.469-474
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• 2009

This paper proposes an real time ray tracing system using optimized kd-tree traversal environment and ray/triangle intersection algorithm. The previous kd-tree traversal algorithms search for the upper nodes in a bottom-up manner. In a such way we need to revisit the already visited parent node or use redundant memory after failing to find the intersected primitives in the leaf node. Thus ray tracing for relatively complex scenes become more difficult. The new algorithm contains stacks implemented on GPU's local memory on CUDA framework, thus elegantly eliminate the problems of previous algorithms. After traversing the node we perform the latest CPU-based ray/triangle intersection algorithm 'Plucker coordinate test', which is further accelerated in massively parallel thanks to CUDA. Plucker test can drastically reduce the computational costs since it does not use barycentric coordinates but only simple test using the relations between a ray and the triangle edges. The entire system is consist of a single ray kernel simply and implemented without introduction of complicated synchronization or ray packets. Consequently our experiment shows the new algorithm can is roughly twice as faster as the previous.

• Journal of Korea Game Society
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• v.13 no.5
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• pp.55-62
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• 2013

Since large terrain data can not be loaded on the GPU or CPU memory at once, out-of-core methods which read necessary part from the secondary storage such as a hard disk are commonly used. However, long delay may occur due to limited bandwidth while loading the data from the hard disk to memory. We propose efficient rendering method of large terrain data, which compresses the data with wavelet technique and save its coefficients in RGBA channel of an image us, then decompresses that in rendering stage. Entire process is performed in GPU using Direct Compute. By reducing the amount of data transfer, performing wavelet computations in parallel and doing decompression quickly on the GPU, our method can reduce rendering time effectively.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.05a
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• pp.11-12
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• 2023

GPGPU 환경에서의 ML 모델이 다양한 분야에 지속적으로 활용되면서, 이미지 분할(image segmentation) 연구가 활발하다. multi-GPU 환경에서 성능 최적화를 위하여 병렬화 기법들이 활용되고 있다. 본 연구에서는 multi-GPU 환경에서 U-Net 모델의 전체 수행 시간을 단축하기 위해 convolution 연산을 최적화하는 기법을 적용하는 실험을 진행하였고 shared memory, data parallelism 를 적용하여 82% 성능 향상을 보여주었다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.4
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• pp.719-726
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• 2015

As big-data and cloud security technologies become popular, many researchers have recently been conducted on faster and lighter encryption. As a result, National Security Research Institute developed LEA which is lightweight and fast block cipher. To date, there have been various studies on lightweight encryption algorithm (LEA) for speeding up using GPU rather than conventional CPU. However, it is rather difficult to explore any guideline how to manipulate the GPU for the efficient usage of the LEA. Therefore, we introduce a guideline which explains how to implement and design the optimal LEA using GPU.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.5
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• pp.656-662
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• 2018

Pattern matching algorithm is widely used in many application fields such as bio-informatics, intrusion detection, etc. Among many string matching algorithms, KMP (Knuth-Morris-Pratt) algorithm is commonly used because of its fast execution time when using large texts. However, the processing speed of KMP algorithm is also limited when the text size increases significantly. In this paper, we propose a high throughput parallel KMP algorithm considering CPU-GPU memory hierarchy based on OpenCL in GPGPU (General Purpose computing on Graphic Processing Unit). We focus on the optimization for the allocation of work-times and work-groups, the local memory copy of the pattern data and the failure table, and the overlapping of the data transfer with the string matching operations. The experimental results show that the execution time of the optimized parallel KMP algorithm is about 3.6 times faster than that of the non-optimized parallel KMP algorithm.

• Journal of Korea Multimedia Society
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• v.19 no.2
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• pp.411-417
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• 2016

Since the development of Graphic Processing Unit (GPU) in 1999, the development speed of GPUs has become much faster than that of CPUs and currently, the computational power of GPUs exceeds CPUs dozens and hundreds times in terms of decimal calculations and costs much less. Owing to recent technological development of hardwares, general-purpose computing and utilization using GPUs are on the rise. Thus, in this paper, we have identified the elements to be considered for the Smart Grid Security. Focusing on a Performance Improvement of the Basic Algorithm for the Stateful Inspection to Detect DDoS Attacks using CUDA. In the program, we compared the search speeds of GPU against CPU while they search for the suffix trees. For the computation, the system constraints and specifications were made identical during the experiment. We were able to understand from the results of the experiment that the problem-solving capability improves when GPU is used. The other finding was that performance of the system had been enhanced when shared memory was used explicitly instead of a global memory as the volume of data became larger.

• Journal of the Korea Society of Computer and Information
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• v.20 no.7
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• pp.9-16
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• 2015

This paper proposes the parallel design of a shot change detection algorithm using frame segmentation and moving blocks. In the proposed approach, the high parallel processing components, such as frame histogram calculation, block histogram calculation, Otsu threshold setting function, frame moving operation, and block histogram comparison, are designed in parallel for NVIDIA GPU. In order to minimize memory access delay time and guarantee fast computation, the output of a GPU kernel becomes the input data of another kernel in a pipeline way using the shared memory of GPU. In addition, the optimal sizes of CUDA processing blocks and threads are estimated through the prior experiments. In the experimental test of the proposed shot change detection algorithm, the detection rate of the GPU based parallel algorithm is the same as that of the CPU based algorithm, but the average of processing time speeds up about 6~8 times.

• KIISE Transactions on Computing Practices
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• v.20 no.9
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• pp.507-512
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• 2014

Recently, Distributed computing processing begins using both CPU(Central processing unit) and GPU(Graphic processing unit) to improve the performance to overcome darksilicon problem which cannot use all of the transistors because of the electric power limitation. There is an integrated graphics processor that CPU and GPU share memory and Last level cache(LLC). But, There is no LLC access rules between CPU and GPU, so if GPU and CPU processes run together at the same time, performance of both processes gets worse because of the contention on the LLC. This Paper gives evidence to prove the need of the Cache Partitioning and is mentioned about the cache partitioning design using page coloring to allocate the L3 Cache space only for the GPU process to guarantee GPU process performance.