• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.686-689
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• 2009

This paper describes a scalar multiplier for Elliptic curve cryptography. The scalar multiplier has 163-bits key size which supports the specifications of smart card standard. To reduce the computational complexity of scalar multiplication on finite field $GF(2^{163})$, the Non-Adjacent-Format (NAF) conversion algorithm based on complementary recoding is adopted. The scalar multiplier core synthesized with a $0.35-{\mu}m$ CMOS cell library has 32,768 gates and can operate up to 150-MHz@3.3-V. It can be used in hardware design of Elliptic curve cryptography processor for smart card security.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.3
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• pp.511-514
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• 2019

Elliptic Curves Cryptosystem(ECC) provides the same level of security with relatively small key sizes, as compared to the traditional cryptosystems. The performance of ECC over GF(2m) and GF(p) depends on the efficiency of finite field arithmetic, especially the modular multiplication which is based on the reduction algorithm. In this paper, we propose a new modular reduction algorithm which provides high-speed ECC over NIST prime P-256. Detailed experimental results show that the proposed algorithm is about 25% faster than the previous methods.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.5_6
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• pp.324-329
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• 2003

The public-key cryptosystems such as Diffie-Hellman Key Distribution and Elliptical Curve Cryptosystems are built on the basis of the operations defined in GF(2$^{m}$ ):addition, subtraction, multiplication and multiplicative inversion. It is important that these operations should be computed at high speed in order to implement these cryptosystems efficiently. Among those operations, as being the most time-consuming, multiplicative inversion has become the object of lots of investigation Formant's theorem says $\beta$$^{-1}$ =$\beta$$^{2}$sup m/-2/, where $\beta$$^{-1}$ is the multiplicative inverse of $\beta$$\in$GF(2$^{m}$ ). Therefore, to compute the multiplicative inverse of arbitrary elements of GF(2$^{m}$ ), it is most important to reduce the number of times of multiplication by decomposing 2$^{m}$ -2 efficiently. Among many algorithms relevant to the subject, the algorithm proposed by Itoh and Tsujii[2] has reduced the required number of times of multiplication to O(log m) by using normal basis. Furthermore, a few papers have presented algorithms improving the Itoh and Tsujii's. However they have some demerits such as complicated decomposition processes[3,5]. In this paper, in the case of 2$^{m}$ -2, which is mainly used in practical applications, an efficient algorithm is proposed for computing the multiplicative inverse at high speed by using both the factorization formula x$^3$-y$^3$=(x-y)(x$^2$＋xy＋y$^2$) and normal basis. The number of times of multiplication of the algorithm is smaller than that of the algorithm proposed by Itoh and Tsujii. Also the algorithm decomposes 2$^{m}$ -2 more simply than other proposed algorithms.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• Journal of Korea Society of Industrial Information Systems
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• v.12 no.1
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• pp.28-38
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• 2007

In this paper, we implement Microsoft COM software modules for elliptic curve cryptographic applications and analyze its performance. The implemented COM software modules support all elliptic curve key exchange protocols and elliptic curve digital signature algorithm in IEEE 1363 finite fields GF(p) and GF(2m). Since the implemented software modules intend to focus on a component-based software development method, and thus it have a higher productivity and take systematic characteristics to be open outward and to be standardized. Accordingly, it enable a software to be developed easier and faster rather than a method using C library. In addition it support the Microsoft COM interface, we can easily implement secure software applications based on elliptic curve cryptographic algorithms.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.7 no.4
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• pp.127-132
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• 1997

본 논문은 유한체 GF(p)에서 r=2p+1이 2-prime이고, p에 대한 위수(order) m을 가질때, q=r$^{e}$ (e$2)를 연결 정수로 갖는 FCSR의 생성된 출력수열에 대한 선형 복잡도의 하한을 구한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.925-927
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• 2011

본 논문에서는 확장 이진 최대공약수 알고리듬 (Extended Binary GCD algorithm)을 기본으로 GF($2^m$) 상에서 유한체 나눗셈 연산을 위한 고속 알고리듬을 제안하고, 제안한 알고리듬을 기본으로 한 나눗셈 연산기의 FPGA 설계 구현에 관하여 기술한다. 제안한 알고리듬은 Verilog HDL 로 기술하였고, Xilinx FPGA virtex4-xc4vlx15 디바이스를 타겟으로 하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.255-258
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• 2004

Efficient finite field operation in the elliptic curve (EC) public key cryptography algorithm, which attracts much of latest issues in the applications in information security, is very important. Traditional serial finite multipliers root from Mastrovito's serial multiplication architecture. In this paper, we adopt the polynomial basis and propose a new finite field multiplier, inducing numerical expressions which can be applied to exhibit 3 times as much performance as the Mastrovito's. We described the proposed multiplier with HDL to verify and evaluate as a proper hardware IP. HDL-implemented serial GF (Galois field) multiplier showed 3 times as fast speed as the traditional serial multiplier's adding only Partial-sum block in the hardware.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.172-180
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• 2004

In this paper, a parallel Input/Output modulo multiplier, which is applied to AOTP(All One or Two Polynomials) multiplicative algorithm over $GF(3^m)$, has been proposed using neuron-MOS Down-literal circuit on voltage mode. The three-valued input of the proposed multiplier is modulated by using neuron-MOS Down-literal circuit and the multiplication and Addition gates are implemented by the selecting of the three-valued input signals transformed by the module. The proposed circuits are simulated with the electrical parameter of a standard $0.35{\mu}m$CMOS N-well doubly-poly four-metal technology and a single +3V supply voltage. In the simulation result, the multiplier shows 4 uW power consumption and 3 MHzsampling rate and maintains output voltage level in ${\pm}0.1V$.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.695-698
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• 2005

The finite-field multiplication can be applied to the wide range of applications, such as signal processing on communication, cryptography, etc. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cell, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-serial and digit-serial multipliers, the proposed multiplier shows relatively better performance with low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.