• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1012-1015
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• 1992

A gate-turn-off thyristor (GTO) that has a fuction of self-commutation is a device that can be turned on like a thyristor with a single pulse of gate current and turned-off by injecting a negative gate current pulse. GTOs have been in existence almost from the beginning of thyristor era, recently are these devices being developed with large power-handling capabilities and improved performance, and they are gaining popularity In conversion equipment. In this paper, the effects of internal parameters of GTO model using a circuit containing two transistors and three resistors the switching operation and the turn-off snubber characteristics is investigated using SPICE program.

• Proceedings of the KSR Conference
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• 2007.11a
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• pp.1438-1444
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• 2007

Standard Gate Turn Off (GTO) Thyristor drive technology results in inhomogeneous turn-on and turn-off transients which in turn needs costly dv/dt and di/dt snubber circuits. Added to this GTO is bulky in size, needs external cooling, slower switching time etc. The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO technology. Indian Railway has developed first IGBT based traction converter and was commissioned in November 2006. Some of the supremacy of IGBT are smaller in size, no external cooling is required, built in power supply which enhances reliability, lower switching losses which leads to higher efficiency, reduced gate drive, high frequency operation in real time etc. These advantages are highlighted along with IGBT Traction system in operation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.77-83
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• 1994

In this paper we numerically approximated the field-effect mobility of a-Si:H TFT. Field-effect mobility, based on the charge-trapping model and new effective capacitance model in our study, used Chebyshev approximation was approximated as the function of gate potential(gate-to-channel voltage). Even though various external factors are changed, this formula can be applied by choosing the characteristic coefficients without any change of the approximation formula corresponding to each operation region. Using new approximated field-effect mobility formula, the dependences of field-effect mobility on materials and thickness of gate insulator, thickness of a-Si bulk, and operation temperature in inverted staggered-electrode a-Si:H TFT were estimated. By this was the usefulness of new approximated mobility formula proved.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.69.3-69.3
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• 2012

A high-performance low-voltage graphene field-effect transistor (FED array was fabricated on a flexible polymer substrate using solution-processable, high-capacitance ion gel gate dielectrics. The high capacitance of the ion gel, which originated from the formation of an electric double layer under the application of a gate voltage, yielded a high on-current and low voltage operation below 3 V. The graphene FETs fabricated on the plastic substrates showed a hole and electron mobility of 203 and 91 $cm^2/Vs$, respectively, at a drain bias of - I V. Moreover, ion gel gated graphene FETs on the plastic substrates exhibited remarkably good mechanical flexibility. This method represents a significant step in the application of graphene to flexible and stretchable electronics.

• Progress in Superconductivity
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• v.4 no.2
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• pp.127-131
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• 2003

We have designed and measured an SFQ(Single Flux Quantum) OR gate for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we used WRspice, XIC and Lmeter for simulations and layouts. The OR gate was consisted of a Confluence Buffer and a D Flip-Flop. When a pulse enters into the OR gate, the pulse does not propagate to the other input port because of the Confluence Buffer. A role of D Flip-Flip is expelling the data when the clock is entered into D Flip-Flop. For the measurement of the OR gate operation, we attached three DC/SFQs, three SFQ/DCs and one RS Flip -Flop to the OR gate. DC/SFQ circuits were used to generate the data pulses and clock pulses. Input frequency of 10kHz and 1MHzwere used to generate the SFQ pulses from DC/SFQ circuits. Output data from OR gate moved to RS flip -Flop to display the output on the oscilloscope. We obtained bias margins of the D Flip -Flop and the Confluence Buffer from the measurements. The measured bias margins $\pm$38.6% and $\pm$23.2% for D Flip-Flop and Confluence Buffer, respectively The circuit was measured at the liquid helium temperature.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.884-886
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• 2005

In this paper, we have investigated characteristics of current-voltage for double gate MOSFET with main gate and side gate. Investigated current-voltage characteristics of channel length changed len호 of channel from 1${\mu}$m to 3${\mu}$m. Also, compare and analyzed characteristics of changed of operation temperature changing current that is dignity. gate voltage could know 2V that is superior than device characteristics of current voltage characteristic in 77K acts in room temperature when approved.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2006.05a
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• pp.125-129
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• 2006

By advent of NNC(Neural Network Chip), it is possible that process in parallel and discern the importance of signal with learning oneself by experience in external signal. So, the design of general purpose operation unit using VHDL(VHSIC Hardware Description Language) on the existing FPGA(Field Programmable Gate Array) can replaced EN(Expert Network) and learning algorithm. Also, neural network operation unit is possible various operation using learning of NN(Neural Network). This paper present general purpose operation unit using hierarchical structure of EN. EN of presented structure learn from logical gate which constitute a operation unit, it relocated several layer. The overall structure is hierarchical using a module, it has generality more than FPGA operation unit.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.81-87
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• 1989

A cellular array multiplier for performing the multiplication of two elements in the finite field GF($2^m$) is presented in this paper. This multiplier is consisted of three operation part ; the multiplicative operation part, the modular operation part, and the primitive irreducible polynomial operation part. The multiplicative operation part and the modular operation part are composed by the basic cellular arrays designed AND gate and XOR gate. The primitive iirreducible operation part is constructed by XOR gates, D flip-flop circuits and a inverter. The multiplier presented here, is simple and regular for the wire routing and possesses the properties of concurrency and modularity. Also, it is expansible for the multiplication of two elements in the finite field increasing the degree m and suitable for VLSI implementation.

• Journal of Korea Water Resources Association
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• v.45 no.9
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• pp.959-968
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• 2012

HEC-RAS has been applied to simulate water level variation in the Ara waterway during the flood season. To support decision making necessary for operation of the hydraulic structures especially during the flood season, it is important to consider various factors such as water level of the Han River, Gulpo River, and tidal level of the west sea in conjunction with operation of the hydraulic structures such as the Gyulhyun Weir, the West sea gate, and pumping stations. Especially for operation of the west sea gate, the Rule-script option was employed to determine the opening height considering the variation of the water level in the waterway and the west sea simultaneously. For model verification, comparison of water level computed at the upstream and downstream of the regulation weir shows a good agreement with observed data measured during the flood event in September 2010. The HEC-RAS model developed in this study will contribute to support operation of the waterway during the flood season.

• Magazine of the Korean Society of Agricultural Engineers
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• v.45 no.6
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• pp.109-118
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• 2003

As a fundamental research to establish a safety operation plan for irrigation dams, this study presents hydrologic analysis conducted in Sungju Dam watershed based on various rainfall data. Especially those reservoirs without flood control feature are widely exposed to the risk of flooding, a safe and optimized operation program need to be improved against arbitrary flooding. In this study, reservoir routing program was developed and simulated for reservoir runoff estimation using WMS hydrology model. The model simulated the variations of reservoir elevation under the condition of open or closed emergency gate. In case of closed emergency gate, water surface elevation was given as 193.15 m, and this value exceeds the dam crest height by 1.65 m. When the emergency gate is open, the increment of water surface elevation is given as 192.01 m, and this value exceeds dam crest height by 0.57 m. As an alternative plan, dam height increase can be considered for flood control under the PMP (Probable Maximum Precipitation) condition. Since the dam size is relatively small compare to the watershed area, sound protection can be expected from the latter option rather than emergency gate installation.