• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.8
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• pp.1044-1051
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• 2020

The age of quantum computers is coming soon. In order to prepare for the upcoming future, the National Institute of Standards and Technology has recruited candidates to set standards for post quantum cryptography to establish a future cryptography standard. The submitted ciphers are expected to be safe from quantum algorithm attacks, but it is necessary to verify that the submitted algorithm is safe from quantum attacks using quantum algorithm even when it is actually operated on a quantum computer. Therefore, in this paper, we investigate an efficient quantum gate implementation for binary field multiplication of code based post quantum cryptography to work on quantum computers. We implemented the binary field multiplication for two field polynomials presented by Classic McEliece and three field polynomials presented by ROLLO in generic algorithm and Karatsuba algorithm.

• The Magazine of the IEIE
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• v.42 no.7
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• pp.26-38
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• 2015

고집적화를 위한 Floating Gate NAND 개발과정에서 몇 차례 기술적 한계상황에 직면하였었지만, Air-Gap, Double patterning, Multi-level Cell, Error Correction Code과 같은 breakthrough idea 을 활용하여 1Xnm까지 성공적인 scale-down 을 하였고 10nm 까지도 바라보고 있지만, 10nm 미만으로는 적절한 방안을 찾지 못한 상황입니다. CTD 의 3D NAND Flash는 Aspect Ratio, Poly channel의 intrinsic 특성, Data 보존 능력 등 해결 해야 할 issue 들이 남아 있지만, F.G Flash 의 지난 20년간 Lesson-learn 과 Band engineering, Channel Si, PUC 의 요소기술 개발 및 System algorithm 개발, QLC 개발 등을 통하여 F.G Flash를 넘어 지속적인 Cost-down 이 가능할 것입니다.

• The Bulletin of The Korean Astronomical Society
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• v.40 no.2
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• pp.44.1-44.1
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• 2015

We set up a project to make spectrometers for single dish observations of the Korean VLBI Network (KVN), a new future multi-beam receiver of the ASTE (Atacama Submillimeter Telescope Experiment), and the total power (TP) antennas of the Atacama Large Millimeter/submillimeter Array (ALMA). Traditionally, spectrometers based on ASIC (Application-Specific Integrated circuit) and FPGA (Field-Programmable Gate Array) have been used in radio astronomy. It is, however, that a Graphics Processing Unit (GPU) technology is now viable for spectrometers due to the rapid improvement of its performance. A high-resolution spectrometer should have the following functions: poly-phase filter, data-bit conversion, fast Fourier transform, and complex multiplication. We wrote a program based on CUDA (Compute Unified Device Architecture) for a GPU spectrometer. We measured its performance using two GPU cards, Titan X and K40m, from NVIDIA. A non-optimized GPU code can process a data stream of around 2 GHz bandwidth, which is enough for the KVN spectrometer and promising for the ASTE and ALMA TP spectrometers.

• Progress in Superconductivity and Cryogenics
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• v.3 no.2
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• pp.39-43
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• 2001

For several decades researches and development on superconducting magnetic energy storage(SMES) system have been done for efficient electric power management. Korea Electrotechnology Research Institute (KERI) have developed of a 1MJ , 300kVA SMES System for improving power quality in sensitive electric loads. It consists of an IGBT (Insulated Gate Bipolar Transistor) based power conversion module. NbTi mixed matrix conductor superconducting magnet and a cryostat with HTS current leads. We developed the code fro design of a SMES magnet. Which could find the parameters of the SMES magnet having minimum amount of superconductors for the same store denerby. and designed the 1 MJ SMES magnet by using it . And we have design and fabricated cryostat with kA class HTS current leads for a 1 MJ SMES System. This paper describes the design fabrication and test results for a 1MJ SMES System.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1358-1361
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• 2002

In this paper, we propose a new architecture of digital automatic gain control (AGC) for a wideband code division multiple access (WCDMA) receiver. The feature of the proposed architecture is simplicity, in that it does not utilize complicated mathematical functions such as log and its inverse. When the proposed algorithm is implemented using a field programmable gate array (FPGA) device, the number of slices used to implement is 130 over the total of 5120 slices (less than 3%) with 61.44 ㎒ clock. This algorithm has been successfully applied to commercial WCDMA base stations.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.1-7
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• 1997

In tis paper, w eproposed a modeling for direct-sequence spread communication base band modem in RT-level VHDL and implemented in a one-chip VLSI and tested. The transmitter modulates with DQPSK modulation method and spreads a modulated signal with 32-bit PN code into 1.152MHz. The receiver de-spreads a signal using 32-tap matched filter and recovers with DQPSK demodulation method. The digital frequency synthesizer generates the sine signal and the cosine signal of 2.304MHz with ROM tables in the size of 7$\^$*/256 and 6$\^$*/256, respectively. The implemented VLSI has been verified a BER with 10$\^$-4/ at E$\_$b//N$\_$o/ of 13dB with a SPW fixed design model and fabricated in the 0.8.mu.m KG6423 gate array with a VHDL model.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.103-110
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• 2005

We present a powerful error control decoder which can be used in all of the commercial DVD systems. The decoder exploits the error information from the modulation decoder in order to increase the error correcting capability. We can identify that the modulation decoder in DVD system can detect errors more than $60\%$ of total errors when burst errors are occurred. In results, fur a decoded block, error correcting capability of the proposed scheme is improved up to $25\%$ more than that of the original error control decoder. In addition, the more the burst error length is increased, the better the decoder performance. Also, a pipeline-balanced RSPC decoder with a low hardware complexity is designed to maximize the throughput. The maximum throughput of the RSPC decoder is 740Mbps@100MHz and the number of gate counts is 20.3K for RS (182, 172, 11) decoder and 30.7K for RS (208, 192, 17) decoder, respectively

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.111-118
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• 2013

This paper presents implementation of Air protocol analyzer and physical layer design algorithm. The analyzer is a measurement system providing real-time analysis of wireless signals between User Equipment (UE) and Node-B. The implemented system proposed in this paper consists of Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The waveform of Wideband Code Division Multiple Access (WCDMA) has been selected for verification of the proposed system. We designed the analyzer using equalizer algorithm and rake-receiver algorithm. Among various algorithms of designing the equalizer, we have chosen Linear Minimum Mean Square Error (LMMSE) equalizer that uses the inverse of channel matrix. Since the LMMSE equalizer uses the inverse channel matrix, it suffers from a large amount of computational load, while it outperforms most conventional equalizers. In this paper, we introduce an efficient procedure of reducing the computational load required by LMMSE equalizer-based receiver.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.9 no.5
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• pp.28-33
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• 2010

A computer code was developed to simulate all three stages of the injection molding process: filling, packing and cooling by finite element method. The constitutive equation used here was compressible Leonov model. The PVT relationship was assumed to follow the Tait equation. The flow-induced birefringence was related to the calculated flow stresses through the linear stress-optical law. Based on the simulation, the Taguchi method was used to investigate the influences of injection molding conditions on the birefringence of a center gate disk. In addition, the optimal processing conditions were selected to minimize the birefringence and the birefringence difference along the positions of the disk.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2005.09a
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• pp.141-146
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• 2005

In the present study, the characteristic of warpage and flow balance for family mould, which is able to mold parts with different shapes in a mold, is considered. To obtain an optimal gate and runner system, plastic injection molding analysis with commercial code is performed. Design and manufacturing of family mould is then carried out on the basis of this computer aided engineering result. Flow balance and warpage comparisons between experiment and numerical analysis give good agreement with each other. However, it was shown that results of warpage measured by CMM was about $20\~55\%$ lower than those of numerical analysis.