• International Journal of Fuzzy Logic and Intelligent Systems
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• 제3권1호
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• pp.105-111
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• 2003

This paper is researching the storing of 40 different kinds of conditions. Such as, car speed, delay in starting time and the volume of cars in traffic. Through the use of a central nervous networking system or AI, using 10 different intersecting roads. We will improve the green traffic light. And allow more cars to easily flow through the intersections. Now days, with increasing many vehicles on restricted roads, the conventional traffic light creates prove startup-delay time and end-lag-time. The conventional traffic light loses the function of optimal cycle. And so, 30-45% of conventional traffic cycle is not matched to the present traffic cycle. In this paper proposes electro sensitive traffic light using fuzzy look up table method which will reduce the average vehicle waiting time and improve average vehicle speed. Computer simulation results prove that reducing the average vehicle waiting time which proposed considering passing vehicle length for optimal traffic cycle is better than fixed signal method which dosen't consider vehicle length.

• 한국컴퓨터산업학회논문지
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• 제5권9호
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• pp.1005-1016
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• 2004

기존 교통신호등은 최적 교통신호주기기능을 상실했다. 기존 교통신호주기는 현시 교통주기와 30% -45% 가 일치하지 않고 있다. 본 논문에서는 평균 주행속도를 개선하고 평균 승용차 대기시간을 단축하기위해서 전자 교통신호등을 본 논문에서 제안한다. 본 논문에서는 실제 교통상황의 교통량, 출발 지연시간, 자동차속도 등의 40가지 센서 입력조건들을 저장하는 방법을 연구 중이다. 지능형 퍼지 기법을 이용하면, 서로 다른 10개의 교차로에 서 최 적의 녹색시간을 예측할 수 있다. 컴퓨터 모의실험 결과, 자동차 길이를 고려하지 않은 기존 교통신호등보다 . 오프셋 및 평균 자동차 대기시간을 줄일 수 있음이 입증되었다.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}