• 제목/요약/키워드: Formal verification

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소프트웨어 신뢰성 향상을 위한 정형기법 (A Survey on Formal Verification Methods)

  • 주운기;이충호;김중배
    • 한국경영과학회:학술대회논문집
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    • 한국경영과학회 2003년도 추계학술대회 및 정기총회
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    • pp.297-300
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    • 2003
  • This paper considers formal verification methods for enhancing software reliability. The formal method verifies that a software is correctly implemented according to its specification by using a mathematical formalism. This paper presents a partial survey on the formal methods and discusses possible applications for the improved software implementation. Finally, some topics are remarked as further studies.

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STATE TOKEN PETRI NET MODELING METHOD FOR FORMAL VERIFICATION OF COMPUTERIZED PROCEDURE INCLUDING OPERATOR'S INTERRUPTIONS OF PROCEDURE EXECUTION FLOW

  • Kim, Yun Goo;Seong, Poong Hyun
    • Nuclear Engineering and Technology
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    • 제44권8호
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    • pp.929-938
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    • 2012
  • The Computerized Procedure System (CPS) is one of the primary operating support systems in the digital Main Control Room. The CPS displays procedure on the computer screen in the form of a flow chart, and displays plant operating information along with procedure instructions. It also supports operator decision making by providing a system decision. A procedure flow should be correct and reliable, as an error would lead to operator misjudgment and inadequate control. In this paper we present a modeling for the CPS that enables formal verification based on Petri nets. The proposed State Token Petri Nets (STPN) also support modeling of a procedure flow that has various interruptions by the operator, according to the plant condition. STPN modeling is compared with Coloured Petri net when they are applied to Emergency Operating Computerized Procedure. A converting program for Computerized Procedure (CP) to STPN has been also developed. The formal verification and validation methods of CP with STPN increase the safety of a nuclear power plant and provide digital quality assurance means that are needed when the role and function of the CPS is increasing.

정형기법을 이용한 Safety-Critical System 개발 방법론 (Development Methodology of Safety-Critical System Using Formal Method)

  • 성창훈;이나영;오승록;최진영
    • 한국정보과학회:학술대회논문집
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    • 한국정보과학회 2000년도 가을 학술발표논문집 Vol.27 No.2 (1)
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    • pp.486-488
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    • 2000
  • 본 연구는 정형기법을 사용하여 Safety-Critical System의 개발 방법론을 제시한다. Safety-Critical System의 전체적인 개발 과정을 제시하고 Safety-Critical System 중의 하나인 원자력 발전소 시스템 중 Reactor Protection System(RPS)을 정형 명세(Formal Specification)하고 정형 검증(Formal Verification)하는 과정과 그에 따른 각 과정의 Compliance를 확인하는 예를 든다. 여기서 정형 명세에는 Software Cost Reduction(SCR)이하는 도구가 사용되었고, 정형 검증에는 SPIN이, Compliance를 확인하는 데에는 Prototype Verification System(PVS)를 사용하였다.

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임베디드 자바 프로그램의 정형 검증 (Formal Verification of Embedded Java Program)

  • 이태훈;권기현
    • 정보처리학회논문지D
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    • 제12D권7호
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    • pp.931-936
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    • 2005
  • 임베디드 소프트웨어는 크기나 기능면에서 복잡하기 때문에 에러가 숨어있을 확률이 높다. 그래서 에러를 효과적으로 찾아낼 수 있는 방법이 절실히 요구된다. 임베디드 소프트웨어에서 잠재적인 오류를 찾아내는 기술중의 하나가 모델 체킹이며, 대표적인 연구로서 SLAM 이 있다. SLAM은 임베디드 C 프로그램의 안전성 속성을 검증하는 소프트웨어 모델 체킹 도구이다. 본 논문에서는 임베디드 자바 프로그램을 검증하는 모델 체킹 도구를 개발했다. SLAM과는 달리 자바 프로그램의 안전성뿐만 아니라 궁극성 속성을 모두 검증할 수 있다. 개발된 모델 체킹 도구를 이용하여 레고 로봇을 제어하는 임베디드 자바 프로그램의 속성을 검증하였다.

PVS를 이용한 수정된 BLP 모델의 안전성 검증 (A Safety Verification of the Modified BLP Model using PVS)

  • 구하성;박태규;송호근
    • 한국정보통신학회논문지
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    • 제10권8호
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    • pp.1435-1442
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    • 2006
  • 안전성에 대한 이상적인 평가방법은 운영체제내의 모든 가능한 연산을 대상으로 실행 결과의 안정성 여부를 검사하는 것이다. 하지만 이는 현실적으로 불가능하다. 그러나 정형기법을 사용할 경우 운영체제 동작논리상의 안전성 보장 여부를 이론적으로 증명할 수 있다. 따라서 본 논문에서는 보안커널의 안정성 검증방법에 대하여 논하고, 정형검증의 대표적인 도구들에 대하여 비교분석을 수행하였다. 그리고 보안커널에 기반한 다중레벨 접근통제모델인 수정된 BLP(Bell & LaPadula) 모델을 검증하기에 적합한 PVS(Prototype Verification System) 검증도구를 선정하였다. 마지막으로 PVS 검증도구를 활용하여 정형명세를 작성하고, 작성된 정형명세의 검증을 통하여 수정된 BLP 모델이 안전한 보안모델이라는 것을 검증하였다.

Formal Verification of Twin Clutch Gear Control System

  • Muhammad Zaman;Amina Mahmood;Muhammad Atif;Muhammad Adnan Hashmi;Muhammad Kashif;Mudassar Naseer
    • International Journal of Computer Science & Network Security
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    • 제24권3호
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    • pp.151-159
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    • 2024
  • Twin clutch model enables the power-shifts as conventional planetary automatic transmission and eradicates the disadvantages of single clutch trans- mission. The automatic control of the dual clutches is a problem. Particularly to control the clutching component that engages when running in one direction of revolution and disengages when running the other direction, which exchange the torque smoothly during torque phase of the gearshifts on planetary-type automatic transmissions, seemed for quite a while hard to compensate through clutch control. Another problem is to skip gears during multiple gearshifts. However, the twin clutch gear control described in ["M Goetz, M C Levesley and D A Crolla. Dynamics and control of gearshifts on twin clutch transmissions, Proceedings of the Institution of Mechanical Engineers, Part D: Journal of Automobile Engineering 2005"], a significant improvement in twin clutch gear control system is discussed. In this research our objective is to formally specify the twin clutch gear control system and verify it with the help of formal methods. Formal methods have a high potential to give correctness estimating techniques. We use UPPAAL for formal specification and verification. Our results show that the twin clutch gear control model partially fulfills its functional requirements.

정형성 기반 국방 안전/보안필수 소프트웨어 개발 및 인증 기준 - 안전/보안필수 소프트웨어 인증 프로세스에 대한 정형기법 적용 방안 연구 - (Formalism-Based Defense Safety/Security-Critical Software Development & Certification Criteria - Application of Formal Methods to Safety/Security-Critical Software Certification Process Activities -)

  • 김창진;최진영
    • 한국군사과학기술학회지
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    • 제10권1호
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    • pp.55-69
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    • 2007
  • The paper provides the approach to apply formal methods to the development and certification criteria of defense safety/security-critical software. RTCA/DO-178B is recognized as a do facto international standard for airworthiness certification but lack of concrete activities and vagueness of verification/certification criteria have been criticized. In the case of MoD Def Stan 00-55, the guidelines based on formal methods are concrete enough and structured for the defense safety-related software. Also Common Criteria Evaluation Assurance Level includes the strict requirements of formal methods for the certification of high-level security software. By analyzing the problems of DO-178B and comparing it with MoD Def Stan 00-55 and Common Criteria, we identity the important issues In safety and security space. And considering the identified issues, we carry out merging of DO-178B and CC EAL7 on the basis of formal methods. Also the actual case studies for formal methods applications are shown with respect to the verification and reuse of software components.

객체 모델 선택을 위한 검증 및 검색방법 (The Verification and Retrieval Method for selection of Compatible Object Model)

  • 임명재;권영만;강정진
    • 한국인터넷방송통신학회논문지
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    • 제9권5호
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    • pp.169-174
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    • 2009
  • 본 논문에서는 정확한 분석 모델을 제시할 수 있는 객체 모델링과 정형화 방법을 통해 개발자와 사용자간 효과적인 의사소통을 제공하고 객체모델의 정형화와 표준화에 필요한 형식명세로의 변환 규칙을 제안한다. 사용자의 요구에 따라 최적의 객체모델 선택을 위한 객체 모델 검색 프로토타입을 제시한다. 이를 통해서 적합한 모델을 선택할 수 있으므로 소프트웨어 개발시 비용과 노력을 최소화할 수 있다.

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정형기법을 이용한 PLC RTOS 검증 (PLC Real Time OS Verification & Validation in Formal Methods)

  • 최창호;송승환;윤동화;황성재
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2005년도 제36회 하계학술대회 논문집 D
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    • pp.2489-2491
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    • 2005
  • Currently, Programmable Logic Contorller(PLC) uses Real Time Operation System(RTOS) as basic OS. RTOS executes defined results as to defined time. General features of RTOS emphasize the priority in each task, high-speed process of external interrupt, task scheduling, synchronization in task, the limitation of memory capacity. For safety critical placement, PLC software needs Verification and Validation(V&V). For example, nuclear power plant. In this paper, PLC RTOS is verified by formal methods. Particularly, formal method V&V uses verification tool called 'STATEMATE', and shows the results.

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Formal Analysis of Distributed Shared Memory Algorithms

  • Muhammad Atif;Muhammad Adnan Hashmi;Mudassar Naseer;Ahmad Salman Khan
    • International Journal of Computer Science & Network Security
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    • 제24권4호
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    • pp.192-196
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    • 2024
  • The memory coherence problem occurs while mapping shared virtual memory in a loosely coupled multiprocessors setup. Memory is considered coherent if a read operation provides same data written in the last write operation. The problem is addressed in the literature using different algorithms. The big question is on the correctness of such a distributed algorithm. Formal verification is the principal term for a group of techniques that routinely use an analysis that is established on mathematical transformations to conclude the rightness of hardware or software behavior in divergence to dynamic verification techniques. This paper uses UPPAAL model checker to model the dynamic distributed algorithm for shared virtual memory given by K.Li and P.Hudak. We analyse the mechanism to keep the coherence of memory in every read and write operation by using a dynamic distributed algorithm. Our results show that the dynamic distributed algorithm for shared virtual memory partially fulfils its functional requirements.