• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2010년도 춘계학술대회
• /
• pp.809-811
• /
• 2010

3차원 그래픽 응용이 가능한 소형 모바일 기기에서의 부동소수점 연산 처리는 전력소모가 많고 하드웨어 비용이 많이 들며 연산 해상도가 너무 정확한 연산보다는 적절한 해상도를 확보하되 하드웨어 자원을 적게 소모하고 전력소모가 낮을수록 바람직하다. 비용이 많이 소요되는 부동소수점 연산은 곱셈과 나눗셈이며, 로그 변환을 이용하면 곱셈과 나눗셈을 덧셈과 뺄셈으로 변환하여 고속 동작을 구현할 수 있으며, 이는 로그 함수값을 얼마나 실제값에 근사화 시킬 수 있는지에 따라 성능이 좌우된다. 본 연구에서는 이러한 고속 부동소수점 연산에 적용될 수 있는 로그변환 회로에 대한 동향을 조사하되, 설계 시 중요하게 고려해야 할 점과 로그변환 회로가 어떻게 근사화되고 적용될 수 있는지에 대하여 상세히 분석한다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
• /
• pp.165-168
• /
• 2001

This paper presents a design of a divide unit supporting IEEE-754 floating point standard single-precision with 32-bit word length. Its functions have been verified with ALTERA MAX PLUS II tool. For a high-speed division operation, the radix-4 non-restoring algorithm has been applied and CLA(carry-look -ahead) adders has been used in order to improve the area efficiency and the speed of performance for the fraction division part. The prevention of the speed decrement of operations due to clocking has been achieved by taking advantage of combinational logic. A quotient select block which is very complicated and significant in the high-radix part was designed by using P-D plot in order to select the fast and accurate quotient. Also, we designed all division steps with Gate-level which visualize the operations and delay time.

• 한국산학기술학회논문지
• /
• 제11권1호
• /
• pp.175-181
• /
• 2010

본 논문에서는 H.264 방식의 full HD실시간영상압축을 위한 율제어 모듈의 새로운 구조를 제안한다. 제안된 구조에서는 각 매크로블록 라인(full HD의 경우 120 매크로 블록, CIF 의 경우 22 매크로 블록)을 따라 율제어 알고리즘을 사용함으로서 QP 가 변경된다. JM의 H.264 율제어 알고리듬에는 복잡한 산술연산과 부동 소숫점 연산을 가지고 있기 때문에, 정수형 산술 CPU 를 통한 율제어 알고리듬의 구현은 불가능하다. 따라서 우리는 부동 소숫점 연산 유닛을 채용하고, 이 부동소숫점 연산 유닛을 이용하여, 율제어 알고리듬을 구현하였으며, 이 하드웨어를 통하여 실시간에 동작할 수 있음을 확인하였다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
• /
• pp.365-368
• /
• 2001

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It peformed the division and square-root by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• 한국정보통신학회논문지
• /
• 제19권10호
• /
• pp.2341-2349
• /
• 2015

부동소수점 나눗셈에서 많이 사용하는 골드스미트 부동소수점 나눗셈 알고리즘은 한 회 반복에 두 번의 곱셈을 수행한다. 본 논문에서는 한 회 반복에 K 번 곱셈을 수행하는 가칭 오차 교정 K차 골드스미트 부동소수점 나눗셈 알고리즘을 제안한다. 본 논문에서 제안한 알고리즘은 입력 값에 따라서 곱셈 횟수가 다르므로, 평균 곱셈 횟수를 계산하는 방식을 유도하고, 여러 크기의 근사 역수 테이블에서 단정도실수 및 배정도실수의 나눗셈 계산에 필요한 평균 곱셈 횟수를 계산한다. 또한 한 번의 곱셈과 판정으로 나눗셈 결과를 보정하는 알고리즘을 제안한다. 본 논문에서 제안한 알고리즘은 오차가 일정한 값보다 작아질 때까지만 반복 연산을 수행하므로 나눗셈 계산기의 성능을 높일 수 있다. 또한 최적의 근사 테이블을 구성할 수 있다.

• 한국환경복원기술학회지
• /
• 제4권1호
• /
• pp.57-66
• /
• 2001

The floating islands have been constructed for the water quality improvement and the biodiversity conservation in an disturbed aquatic ecosystem. We made floating islands consisted of a special float and substrates of coconut fibers implanted with four emergent macrophytes such as Phragmites australis, Zizania latifolia, Iris pseudoacorus, Typha angustifolia. Vegetation structure and plant growth were compared between on the floating islands and on ground in order to select suitable plants for the construction of floating islands. Emergent-macrophytic vegetation on the floating islands showed lower coverages and higher plant biodiversity due to natural introduction of various hydrophytes and hygrophytes. Shoot density was increased on floating islands except for Zizania latifolia. From the point of coverage and density of plants, Phragmites australis and Iris pseudoacorus were suitable for floating islands. Total biomass of emergent macrophytes was decreased on the floating islands. The belowground/aboveground biomass ratio of floating islands was higher than that of the ground. Out of planted macrophytes, Iris pseudoacorus with a high belowground/aboveground biomass ratio could be evaluated a suitable plant for the floating islands because a plenty of its root is profitable to adapt with the nutrient-limited environment of floating islands.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
• /
• pp.353-356
• /
• 2000

In this paper, a high-performance and small-area floating-point divider, which is suitable for embedded processors and supports all rounding modes defined by IEEE 754 standard, is designed using the series expansion algorithm. This divider shares and fully utilizes the two MAC units for quadratical convergence to the correct quotient. The area increase of two MAC units due to the division is minimized in this design, so that it can be suitable for embedded processors. The tested HDL codes are synthesized and optimized with 0.35$\mu\textrm{m}$ CMOS standard celt libraries. The results show that the latency of the synthesized divider is 17.43 ㎱ in worst condition. But, the divider calculates the correct rounded quotient through only 6 cycles.

• 한국수산과학회지
• /
• 제43권2호
• /
• pp.159-168
• /
• 2010

This paper presents a mathematical model and simulation method for investigating the performance of set net systems and fish cage systems influenced by currents and waves. Both systems consist of netting, mooring ropes, a floating collar and sinkers. The netting and ropes were considered flexible structures and the floating collar was considered an elastic structure. Both were modeled on a mass-spring model. The structures were divided into finite elements and mass points were placed at the mid-point of each element, and the mass points were connected by mass-less springs. Each mass point was subjected to external and internal forces and the total force was calculated at every integration step. An implicit integration scheme was used to solve the nonlinear dynamic system. The computation method was applied to dynamic simulation of actual systems simultaneously influenced by currents and waves in order to evaluate their practicality. The simulation results improved our understanding of the behavior of the structure and provided valuable information concerning the optimized design of set net and fish cage systems exposed to an open ocean environment.

• Journal of Advanced Marine Engineering and Technology
• /
• 제38권2호
• /
• pp.195-201
• /
• 2014

Flexible risers have been used extensively in recent years for floating and early production systems. Such risers offer the advantage of having inherent heave compliance in their catenary thereby greatly reducing the complexity of the riser-to-rig and riser-to subsea interfaces. Another advantage with flexible risers is their greater reliability. Concerns about fatigue life, gas permeation and pigging of lines have been overcome by extensive experience with these risers in production applications. In this paper, flexible riser analysis results were compared through coupled and uncoupled dynamic analyses methods. A time domain coupled analysis capability has been developed to model the dynamic responses of an integrated floating system incorporating the interactions between vessel, moorings and risers in a marine environment. For this study, SPM (Single Point Mooring) system for an FSU in shallow water was considered. This optimization model was integrated with a time-domain global motion analysis to assess both stability and design constraints of the flexible riser system.

• 대한전자공학회논문지TE
• /
• 제37권5호
• /
• pp.7-16
• /
• 2000

본 논문은 고속 지수 선택기를 이용한 여분 부동 소수점 이진수의 제산/스퀘어-루트 설계 및 구현에 관하여 기술하였다. 본 제산/스퀘어-루트는 처리 속도 25㎒를 갖는 여분 이진수의 가산 방식을 사용하여 올림수 지연을 제거함으로써 비트 크기에 관계없이 일정한 시간으로 가산을 수행한다. 각각의 반복 단계에 널리 사용된 제산과 스퀘어-루트에 대해 16-비트 VLSI 회로를 설계하였다. 이것은 매번 16개 클럭마다 시프트된 이진수를 여분 가산하여 제산 및 스퀘어-루트를 실행한다. 또한 이 회로는 비복원 방법을 사용하여 지수 비트를 얻는다. 지수 선택 논리의 간단한 회로를 구현하기 위하여 나머지 비트의 주요 세 자리를 사용하였다. 결과적으로, 이 회로의 성능은 새로운 지수 선택 가산 논리를 적용하여 지수 결정 영역을 병렬 처리함으로써 한층 더 연산 처리 속도를 높인 것이다. 이전에 동일한 알고리즘을 사용하여 제안된 설계보다 13% 빠른 속도 증가를 보였다.