• Journal of the Microelectronics and Packaging Society
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• v.13 no.2 s.39
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• pp.21-26
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• 2006

We developed a bonding at low temperature using fine pitch Sn and In bumps, and studied the reliability of the fine pitch In-Sn solder joints. The $30{\mu}m$ pitch Sn and In bumps were joined together at $120^{\circ}C$. A non conductive adhesive (NCA) was applied during solder joining. Thermal cycling test ($0^{\circ}C-100^{\circ}C$, 2 cycles/h) of up to 2000 cycles was carried out to evaluate the reliability of the solder joints. The bondability was evaluated by measuring the contact resistance (Rc) of the joints through the four point probe method. As the content of filler increased, the reliability improved in the solder joints during thermal cycling test because the contact resistance increased little. The filler redistributed the stress and strains from the thermal shock over the entire joint area.

• Proceedings of the KSME Conference
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• 2007.05b
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• pp.2449-2452
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• 2007

Hot spots on thin wafers of IC packages are becoming important issues in thermal and electrical engineering fields. To investigate these hot spots, we developed a Diode Temperature Sensor Array (DTSA) that consists of an array of 32 ${\times}$32 diodes (1,024 diodes) in a 8 mm ${\times}$ 8 mm surface area. To know specifically the hot spot temperature which is affected by the chip thickness and a generated power, we made the DTSA chips, which have 21.5 ${\mu}m$, 31 ${\mu}m$, 42 ${\mu}m$, 100 ${\mu}m$, 200 ${\mu}m$, and 400 ${\mu}m$ thickness using the CMP process. And we conducted the experiment using various heater power conditions (0.2 W, 0.3 W, 0.4 W, 0.5 W). In order to validate experimental results, we performed a numerical simulation. Errors between experimental results and numerical data are less than 4%. Finally, we proposed a correlation for the hot spot temperature as a function of the generated power and the wafer thickness based on the results of the experiment. This correlation can give an easy estimate of the hot spot temperature for flip chip packaging when the wafer thickness and the generated power are given.

• Proceedings of the KSME Conference
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• 2004.11a
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• pp.1231-1235
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• 2004

The needs of micro scale thermal detecting technique are increasing in biology and chemical industry. For example, Thermal finger print, Micro PCR(polymer chain reaction), ${\mu}TAS$ and so on. To satisfy these needs, we developed a DTSA(Diode Temperature Sensor Array) for detecting and controlling the temperature on small surface. The DTSA is fabricated by using VLSI technique. It consists of 32 ${\times}$ 32 array of diodes (1,024 diodes) for temperature detection and 8 heaters for temperature control on a 8mm ${\times}$ 8mm surface area. The working principle of temperature detection is that the forward voltage drop across a silicon diode is approximately proportional to the inverse of the absolute temperature of diode. And eight heaters ($1K{\Omega}$) made of poly-silicon are added onto a silicon wafer and controlled individually to maintain a uniform temperature distribution across the DTSA. Flip chip packaging used for easy connection of the DTSA. The circuitry for scanning and controlling DTSA are also developed

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.109-112
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• 1996

The more integrated and smaller SMD are needed, new solder joints packaging technologies are developed in these days such as BGA(Ball Grid Array), Flip Chip, J-lead etc. But, it's unable to inspect solder joints in those devices by visual inspection methods, because they are hided by it's packages. To inspect those new SMD packages, an X-ray system for acquiring a cross-sectional image of a arbitrary plane is necessary. In this paper, an analysis for designing X-ray cross sectional imaging system is presented including the way for correcting the distortion of image intensifier. And we show computer simulation of that system with a simple PCB model to show it's usefulness in applying PCB solder joint inspection.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.1005-1008
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• 2003

We report a new FCOG (flip chip on glass) technique using solder bumps for display packaging applications. The In and Sn solder bumps of 40 ${\mu}m$ pitches were formed on Si and glass substrate. The In and Sn bumps were bonded at 125 at the pressure of 3 mN/bump. The metallurgical bonding was confirmed using cross-sectional SEM. The contact resistance of the solder joint was 65 $m{\Omega}$ which was much lower than that of the joint made using the conventional ACF bonding technique. We demonstrate that the new COG technique using solder bump to bump direct bonding can be applied to advanced LCDs that lead to require higher quality, better resolution, and lower power consumption.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.146-149
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• 2007

1) 자체 제작한 NCP인 A, B, C 3종은 상용화 제품에 비해 도포성에 관련한 특성은 우수한 것으로 나타났으나 Tg 등의 열특성은 개선이 필요한 것으로 판단된다. 2) 접합강도의 경우 4종의 큰 차이가 없었으나 필러가 비교적 적은 조성인 B 조성의 경우 가장 큰 접합강도를 나타냈다. 3) NCP A, B, C 3종에 대한 접속저항 측정 결과 필러가 가장 많은 C의 경우가 가장 높은 저항 값을 보였으며 이는 가속 고온 고습 시험에 대한 결과에서도 급격한 접속률 감소를 통해 확인할 수 있다. 4) 시간에 따른 접속저항의 급격한 증가는 NCP 성분 중 친수성을 가진 물질이 있는 것이 원인이라 판단되며 이에 대한 개선을 통해 고습에 대한 신뢰성을 향상시킬 수 있을 것으로 보인다.

• Electronics and Telecommunications Trends
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• v.33 no.6
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• pp.50-57
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• 2018

As devices have evolved, traditional flip chip bonding and recently commercialized thermocompression bonding techniques have been limited. Laser-assisted bonding is attracting attention as a technology that satisfies both the requirements of mass production and the yield enhancement of advanced packaging interconnections, which are weak points of these bonding technologies. The laser-assisted bonding technique can be applied not only to a two-dimensional bonding but also to a three-dimensional stacked structure, and can be applied to various types of device bonding such as electronic devices; display devices, e.g., LEDs; and sensors.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.2
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• pp.47-53
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• 2000

The fluxless wetting properties of TSM-coated glass substrate were evaluated by the wetting balance method. We could estimate the wettability of the TSM with new parameters obtained from the wetting balance test for one side-coated specimen. It was more effective in wetting to use Cu as a wetting layer and Au as a protection layer than to use Au itself as a wetting layer. The SnSb solder showed better wettability than SnAg, SnBi, and SnIn solders. The contact angle of the one side-coated glass substrate to the Pb-free solders could be calculated from the farce balance equation by measuring the static force and the tilt angle.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.45-50
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• 2012

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.33-38
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• 2013

In this study, both a finite element analysis and an experimental analysis are executed to investigate the mechanical characteristics of dielectric material effects on warpage. Also, viscoelastic material properties are measured by DMA and are considered in warpage simulation. A finite element analysis is done by using both thermal elastic analysis and a thermo-viscoelastic analysis to predict the nonlinear effects. For experimental study, specimens warpage of non-symmetric structure with body size of $22.5{\times}22.5$ mm, $37.5{\times}37.5$ mm and $42.5{\times}42.5$ mm are measured under the reflow temperature condition. From the analysis results, experimental warpage is not similar to FEA results using thermal elastic analysis but similar to FEA results using thermo-viscoelastic analysis. Also, its effect on substrate warpage is increased as core thickness is decreased and body size is getting larger. These FEA and the experimental results show that the nonlinear characteristics of dielectric material play an important role on substrate warpage. Therefore, it is strongly recommended that non-linear behavior characteristics of a dielectric material should be considered to control warpage of FCBGA substrate under conditions of geometry, structure and manufacturing process and so on.