• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.43-45
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• 2004

This paper represents the improvement of floating point operation for AC servo motor controller based on fixed point operation DSP. TMS320F2812 has fixed point operation processing structure. The controller parameters are modified to the digitized data by scaling the original parameters. TMS320F 2812 is a 32-bit processor, and it could have enough accuracy to get the digitized data this procedure is implemented and the experiments controling a AC servo system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 B
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• pp.1196-1198
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• 2004

This paper represents the improvement of floating point operation for AC servo motor controller based on fixed point operation DSP. TMS320F2812 has fixed point operation processing structure. The controller parameters are modified to the digitized data by scaling the original parameters. TMS320F 2812 is a 32-bit processor, and it could have enough accuracy to got the digitized data this procedure is implemented and the experiments controling a AC servo system.

• 전자공학회논문지A
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• 제29A권3호
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• pp.96-105
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• 1992

The use of fixed-point digital signal processors, such as the TMS 320C25, requires scaling of data at each arithmetic step to prevent overflows while keeping the accuracy. A software which automatizes this process is developed for TMS 320C25. The programmers use a model of a hypothetical floating-point digital signal processor and a floating-point format for data representation. However, the program and data are automatically translated to a fixed-point version by this software. Thus, the execution speed is not sacrificed. A fixed-point variable has a unique binary-point location, which is dependent on the range of the variable. The range is estimated from the floating-point simulation. The number of shifts needed for arithmetic or data transfer step is determined by the binary-points of the variables associated with the operation. A fixed-point code generator is also developed by using the proposed automatic scaling software. This code generator produces floating-point assembly programs from the specifiations of FIR, IIR, and adaptive transversal filters, then floating-point programs are transformed to fixed-point versions by the automatic scaling software.

• 대한전자공학회논문지SP
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• 제46권1호
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• pp.95-103
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• 2009

본 논문에서는 WCDMA RF 중계기 시스템에서 송신안테나에서 전송 증폭된 중계신호가 수신안테나로 귀환되는 현상을 제거하고자 고정 소수점 연산의 ICS 알고리즘을 이용하여 중계기의 성능을 향상시킨다. 귀환 신호의 제거를 위한 LMS 기반의 ICS 알고리즘은 고속 DSP 프로세서나 대용량 FPGA를 사용하며, 이때 부동 소수점 연산을 위한 처리장치는 가격이 고가인 단점이 있다. 본 논문에서는 고정 소수점 연산 프로세서를 사용하여 ICS 알고리즘을 구현할 수 있도록 고정 소수점 연산용 ICS 알고리즘을 개발하고, 알고리즘의 성능검증을 위하여 부동 소수점 연산을 사용한 경우와 비교 시뮬레이션을 수행한다.

• 대한전기학회논문지
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• 제40권4호
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• pp.331-341
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• 1991

The discrete cosine transform (DCT) is widely used in many signal processing areas, including image and speech data compression. In this paper, we investigate a fixed-point error analysis for fast DCT algorithms, namely, Lee [6], Hou [7] and Vetterli [8]. A statistical model for fixed-point error is analyzed to predict the output noise due to the fixed-point implementation. This paper deals with two's complement fixed-point data representation with truncation and rounding. For a comparison purpose, we also investigate the direct form DCT algorithm. We also propose a suitable scaling model for the fixed-point implementation to avoid an overflow occurring in the addition operation. Computer simulation results reveal that there is a close agreement between the theoretical and the experimental results. The result shows that Vetterli's algorithm is better than the other algorithms in terms of SNR.

• 한국철도학회:학술대회논문집
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• 한국철도학회 1999년도 추계학술대회 논문집
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• pp.280-287
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• 1999

An automatic train operation(ATO) system executes the operation of constant speed travelling and fixed point parking by using microprocessors instead of drivers manual operation. This paper describes the mathematical model for the train considering unknown disturbances which consist of start resistance, travelling resistance, slope resistance, curve resistance, and so on. The speed controller of ATO system is designed by considering the disturbances. The simulation is executed to verify the speed control and fixed point parking performance and to compare its performance with that of a PID-type ATO control system under disturbances. Simulation results show that the control performance of gain scheduled control scheme fur ATO system is better than that of the conventional PID controller.

• 한국통신학회논문지
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• 제31권7C호
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• pp.735-742
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• 2006

본 논문에서는 IEEE 802.16e OFDMA(Orthogonal Frequency Division Multiplexing-FDMA) TDD(Time Division Duplexing) 시스템 단말 수신기의 입력 신호에 대하여 DC 오프셋 보상, 자동 주파수 조정, 자동 이득 조정을 수행하는 DFE(Digital Front End)의 동작 원리와 Fixed-point 설계 방법에 대하여 설명하고, DFE의 성능을 ITU-R M. 1225 Veh-A 60km/h 채널 환경에서 시뮬레이션 결과를 통해 분석한다. DFE의 Fixed-point 설계시, 시스템의 성능에 영향을 주지 않는 범위 내에서 연산을 통해 출력되는 bit의 크기를 줄임으로서때 H/W 동작의 복잡도를 줄이고, Acquisition time과 안정도 간의 Trade-off를 고려하여 Loop Filter를 설계함으로서 DFE 의 Fixed-point 설계를 최적화 한다.

• 대한전기학회논문지:시스템및제어부문D
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• 제50권3호
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• pp.114-119
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• 2001

An automatic train operation(ATO) system executes the operation of constant speed travelling and fixed point parking by using microprocessors instead of driver's manual operation. This paper describes the mathematical model for the train considering unknown disturbances which consist of start resistance, travelling resistance, slope resistance, curve resistance, and so on. The speed controller of ATO system is designed by considering the disturbances. The simulation is executed to verify the speed control and fixed point parking performance and to compare its performance with that of a PID-type ATO control system under disturbances. Simulation results show that the control performance of gain scheduled control scheme for ATO system is better than that of the conventional PID controller.

• 한국통신학회논문지
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• 제25권8B호
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• pp.1460-1468
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• 2000

본 논문에서는 고정소수점 DSP인 TMS320C6201을 이용하여 MPEG-1 Layer III 오디오 디코더를 실시간으로 동작하도록 구현하였다 음질의 손실 없이 부동소수점 연산을 고정소수점 연산으로 변환하였으며 적은 메모리를 사용하여 동작하도록 소스프로그램을 최적화하였다 특히 연산의 정확성을 위해서 Descaling 모듈에서 중점적으로 부동소수점 연산을 고정소수점 연산으로 변환하여UT고 연산량과 프로그램 크기를 줄이기 위해서 IMDCT 모듈과 Synthesis Polyphase Filter Bank 모듈에 대해서 최적화 작업을 수행하였다 그 결과 구현된 디코더는 TMS320C6201 DSP가 수행할 수 있는 최대 연산량의 26% 만으로 실시간 동작이 가능하여UT으며 사용된 프로그램 ROM의 크기는 3.13 kWord 데이터 RAM의 크기는 9.94 kWord 이었다 부동소수점 프로그램의 최종 출력 PCM값과 구현된 고정소수점 연산의 최종 출력 PCM값을 비교하여 60 dB 이상의 높은 SNR를 가짐을 확인함으로써 고정소수점 연산의 정확성을 검증하였다. 또한 EVM 보드에서 사운드 입출력과 호스트(PC) 통신을 이용하여 실시간으로 동작함을 확인하였다.

• 대한전기학회논문지:전력기술부문A
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• 제55권12호
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• pp.514-521
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• 2006

The existing ULTC operation control strategy based on the measured data deteriorates the voltage compensation capability making the efficient corresponding to the load variation difficult by following the fixed load center point voltage. Accordingly, this paper proposes a new on-line fuzzy ULTC controller based on the designed multiple load center points which can improve the voltage compensation capability of ULTC and minimize voltage deviation by moving in real-time the load center point according to the load variation to an adequate position among the multiple load center points designed using the clustering technique. The Max-Min distance technique is adopted as the clustering technique for the decision of multiple load points from measured MTr load current and PTr voltage, and the minimum distance classifier is adopted for the decision of fuzzy output membership function. To verify the effectiveness of the proposed strategy, Visual C++ MFC-based simulation environments is developed. Finally, the superiority the proposed strategy is proved by comparing the fuzzy ULTC operation control results based on multiple load center points with the existing ULTC operation control results based on fixed load center point using the data for three day.