• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.13-16
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• 2005

Many mobile communication systems require bandpass filter with sharp skirt characteristics and consequently a filter was formed by more order. It needs to improve flatness in passband. In this paper, amplitude equalizer was used to improve the flatness of passband. We modified Chebyshev prototype filter by use of network synthesis and computed the prototype elements for Shaping filter. We designed and realized a 13-order combline bandpass filter and 4-order amplitude equalizer with coaxial dielectric resonators at WiBro band. The measured results show $\pm$0.82 dB amplitude difference in passband, 6 dB improved flatness.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.3
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• pp.245-252
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• 2010

This paper proposes an improved filter synthesis method for dual-band filters based on coupled lines loaded with shunt stubs. The conventional design method relies on equality of the response of the conventional single-band filter and its dual-band counterpart at two frequencies. On the other hand, the proposed method is based on equivalence of the propagation constants and the image impedances of the two filters. Therefore, the proposed method does not suffer from bandwidth reduction phenomena, which requires complex compensating process in the conventional method. Also, the alternative design parameters provided by the demonstrated method enable to construct dual-band filters with more flexibility. For experimental verification, a Chebyshev type dual-band filter with center frequencies at 1 GHz and 3.5 GHz is designed and fabricated. The measured results are in excellent agreement with the full-wave simulated results.

• The Transactions of the Korea Information Processing Society
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• v.5 no.11
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• pp.2973-2979
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• 1998

As this paper is a scheduling algorithm for the synthesis of a pipelined datapath under resource constraints in high level synthesis, the proposed heuristic algorithm uses a priority function based on the collision count of resourecs. In order to schedule the pipelined datapath under resource constraints, we define the collision count and the priority function based on the collision count, a number of resource, and the mobility of operations to resolve a resource collision. The proposed algorithm supports chaining, multicycling, and structural pipelining to design the realistic hardware. The evaluation of the Performance is compared with other systems using the results of the synthesis for a 16point FIR filter and a 5th order elliptic wave filter, where in most cases, the optimal solution is obtained.

• Proceedings of the IEEK Conference
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• 2000.11d
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• pp.191-194
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• 2000

Frequency domain adaptive filter is effective to communication fields of many computational requirements. In this paper we propose a new variable step size algorithms which improves the convergence speed and reduces computational complexity for frequency domain adaptive filter. we compared MSE of the proposed algorithms with one of normalized FLMS using computer simulation of adaptive noise canceler based on synthesis speech.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.571-574
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• 2000

A complex coefficient filter obtained by directly exchanging several reactance elements included in a real coefficient, filter for imaginary valued resistors is described. By using the proposed method, four varieties of complex coefficient filter are obtained. The stability problem is described. Finally, the frequency responses of the proposed kiters are shown.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.2
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• pp.141-145
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• 2009

A C-to-SystemC synthesizer which processes the input behavior according to high-level synthesis, and then transforms the synthesis result into SystemC module code is implemented in this paper. In the synthesis process, the input behavioral description in C source code is scheduled using list scheduling algorithm and register allocation is performed using left-edge algorithm on the result of scheduling. In the SystemC process, the output from high-level synthesis process is transformed into SystemC module code by combining it with SystemC features such as channels and ports. The operation of the implemented C-to-SystemC synthesizer is validated through simulating the synthesis of elliptic wave filter in SystemC code. C-to-SystemC synthesizer can be used as a part of tool-chain which helps to implement SystemC design methodology covering from modeling to synthesis.

• Proceedings of the Korean Society of Computer Information Conference
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• 2014.01a
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• pp.5-8
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• 2014

This paper presents a parallel approach of formant synthesis method for haegeum on graphics processing units (GPU) using spectral modeling. Spectral modeling synthesis (SMS) is a technique that models time-varying spectra as a combination of sinusoids and a time-varying filtered noise component. A second-order digital resonator by the impulse-invariant transform (IIT) is applied to generate deterministic components and the results are band-pass filtered to adjust magnitude. The noise is calculated by first generating the sinusoids with formant synthesis, subtracting them from the original sound, and then removing some harmonics remained. The synthesized sounds are consequently by adding sinusoids, which are shown to be similar to the original Haegeum sounds. Furthermore, GPU accelerates the synthesis process enabling- real time music synthesis system development, supporting more sound effect, and multiple musical sound compositions.

• Proceedings of the KIEE Conference
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• 1979.08a
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• pp.29-31
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• 1979

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1988.10a
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• pp.227-232
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• 1988

• The Transactions of the Korea Information Processing Society
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• v.2 no.1
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• pp.106-118
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• 1995

In this work, the optimized design methodology in high-level synthesis related with scheduling and hardware allocation is developed by simulated annealing technique effectively modified . Applying this method to digital filter design, the optimized tradeoff problem of speed and hardware costs in pipelined digital filter case and array digital filter case are investigated. While, it is confirmed that the suggested method gives the improved cost function value faster and can be used in complicated digital filter design.