• 제목/요약/키워드: Film Capacitor

검색결과 454건 처리시간 0.025초

HfO2/Hf/Si MOS 구조에서 나타나는 HfO2 박막의 물성 및 전기적 특성 (Electrical and Material Characteristics of HfO2 Film in HfO2/Hf/Si MOS Structure)

  • 배군호;도승우;이재성;이용현
    • 한국전기전자재료학회논문지
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    • 제22권2호
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    • pp.101-106
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    • 2009
  • In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.

나노입자 자기조립 단일층을 이용한 유기메모리 소자 (Organic Memory Device Using Self-Assembled Monolayer of Nanoparticles)

  • 정헌상;오세욱;김예진;김민근;이현호
    • 공업화학
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    • 제23권6호
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    • pp.515-520
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    • 2012
  • 이 총설에서는 개별인식 태그와 바이오센서 등에 사용가능성이 높은 실리콘 기반의 캐패시터와 유기 박막트랜지스터 소자의 제작과 차이점이 논하여 진다. 금속이나 혹은 비금속의 나노입자는 화학물질이나 혹은 바이오분자, 즉, 단백질과 올리고 DNA 등에 표면이 싸여질 수 있으며, 상응하는 목표 바이오분자가 결합되어져 있는 절연체에 자기조립 단일층을 형성할 수 있다. 단일층으로 형성된 나노입자는 정전하 기본단위로서 유기 메모리 소자의 나노 플로팅 게이트로서 역할을 하는 것이다. 특히, 바이오분자의 선택적이고 강한 결합 메카니즘을 통하여도, 메모리 캐패시터나 유기 메모리 박막트랜지스터가 성공적으로 시연되었다. 더불어, 이러한 유기 메모리 소자는 차후 유연기판의 유기전자소자 영역의 발전을 촉진할 것으로 기대된다. 또한, 유기 메모리 박막트랜지스터는 앞으로 새로운 개념의 소자로의 적용이 가능하다.

ALD 방법으로 증착된 $HfO_2$/Hf 박막을 게이트 절연막으로 사용한 MOS 커패시터 제조 (The Fabrication of MOS Capacitor composed of $HfO_2$/Hf Gate Dielectric prepared by Atomic Layer Deposition)

  • 이대갑;도승우;이재성;이용현
    • 대한전자공학회논문지SD
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    • 제44권5호
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    • pp.8-14
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    • 2007
  • 본 논문에서는 MOS 소자의 게이트 유전체로 사용될 고유전 박막으로 $HfO_2$/Hf 박막을 제조하여 그 전기적 특성을 관찰하였다. $HfO_2$박막은 TEMAH와 $O_3$ 전구체를 사용한 ALD 방법으로 p-type (100) 실리콘 웨이퍼 위에 증착하였다. $HfO_2$막을 증착시키기 전에 중간층으로써 Hf 금속 층을 증착하였다. Round-type의 MOS 커패시터 제작을 위해, 상부 전극은 Al 또는 Pt을 이용하여 약 2000 ${\AA}$ 두께의 전극을 형성하였다. $HfO_2$ 박막은 화학정량적 특성을 보였으며, $HfO_2$/Si 계면에서 Si-O 결합 대신 Hf-Si 결합과 Hf-Si-O 결합이 관찰되었다. $HfO_2$와 Si 사이의 Hf 중간층은 $SiO_x$의 성장이 억제되었고, $HfSi_xO_y$으로 변형되었다. 이러한 결과로 $HfO_2$/Hf/Si 구조에서 Hf 중간층이 있음으로 게이트 유전체의 고유전율이 유지되면서 계면 특성이 개선됨을 확인하였다.

Fabrication of Inkjet-printed and Non-sintered $BaTiO_3$ Dielectric Film

  • Lim, Jong-Woo;Kim, Ji-Hoon;Kim, Hyo-Tea;Yoon, Young-Joon;Yoon, Ho-Gyu;Kim, Jong-Hee
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 추계학술대회 논문집
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    • pp.80-80
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    • 2009
  • $BaTiO_3$ has high permittivity so that has been applied to dielectric and insulator materials in 3D system-level package integration. In order to achieve excellent performance of device, the $BaTiO_3$ layer should be highly dense. In this study, $BaTiO_3$ thick films were prepared by the inkjet printing method using 4 vol.% $BaTiO_3$ colloidal inks and cured at $28^{\circ}C$ for 5 h after infiltration of polymer resin for non-sintered process using 3 vol.% cyanate ester emulsion ink. From the obtained results. packing density was determined to be improved by overlapping rabbit ears which were generated by coffee ring effect. We also calculated the packing densities of the films and correlated these packing densities to the measured permittivity of the films.

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Dielectric $Bi_3NbO_7$ thin film grown on flexible substrates by Nano Cluster Deposition

  • Lee, Hyun-Woo;Yoon, Soon-Gil
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 추계학술대회 논문집
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    • pp.10-10
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    • 2009
  • Transparent BNO thin films were grown on Al-doped ZnO (AZO)/Ag/AZO/polyethersulfon (PES) (abbreviated as AAAP) transparent electrodes at a low temperature by the NCD technique. The BNO films grown on the crystallized AZO/Ag/AZO (AAA) electrodes exhibit an amorphous phase with a root mean square (rms) roughness of approximately 2 nm in the range of deposition temperature. The capacitors (Pt/BNO/AAAP) with BNO films grown at $100^{\circ}C$ show a dielectric constant of 24 and dissipation factor of 8% at 100 kHz, a leakage current density of about $8{\times}10^{-6}A/cm^2$ at an applied voltage of 1.0V. The optical transmittances of the BNO/AAAP exhibited above 80% at wavelength of 550nm at all of deposition temperature. The mechanical stability of the BNO/AAA as well as AAA electrode with the PES substrates through the bending was ensured for flexible electronic device applications. The transparent BNO capacitors grown on AAAP are powerful candidate for integration with the transparent solar cells.

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Hysteresis-free organic field-effect transistors with ahigh dielectric strength cross-linked polyacrylate copolymer gate insulator

  • Xu, Wentao;Lim, Sang-Hoon;Rhee, Shi-Woo
    • 한국재료학회:학술대회논문집
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    • 한국재료학회 2009년도 추계학술발표대회
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    • pp.48.1-48.1
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    • 2009
  • Performance of organic field-effect transistors (OFETs) with various temperature-cured polyacrylate(PA) copolymer as a gate insulator was studied. The PA thin film, which was cured at an optimized temperature, showed high dielectric strength (>7 MV/cm), low leakage current density ($5{\times}10^{-9}\;A/cm^2$ at 1 MV/cm) and enabled negligible hysteresis in MIS capacitor and OFET. A field-effect mobility of ${\sim}0.6\;cm^2/V\;s$, on/off current ratio (Ion/Ioff) of ${\sim}10^5$ and inverse subthreshold slope (SS) as low as 1.22 V/decwere achieved. The high dielectric strength made it possible to scale down the thickness of dielectric, and low-voltage operation of -5 V was successfully realized. The chemical changes were monitored by FT-IR. The morphology and microstructure of the pentacene layer grown on PA dielectrics were also investigated and correlated with OFET device performance.

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Electrical Characteristics of $(Ba,Sr)TiO_3/RuO_2$ Thin films

  • Park Chi-Sun
    • 마이크로전자및패키징학회지
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    • 제11권3호
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    • pp.63-70
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    • 2004
  • The structural, electrical properties of $(Ba, Sr)TiO_3[BSTO]/RuO_2$ thin films were examined by the addition of amorphous BSTO layer between crystlline BSTO film and $RuO_2$ substrate. We prepared BSTO films with double-layered structure, that is, amorphous layers deposited at $60^{\circ}C$ and crystalline films. Crystalline films were prepared at 550 on amorphous BSTO layer. The thickness of the amorphous layers was varied from 0 to 170 nm. During the deposition of crystalline films, the crystallization of the amorphous layers occurred and the structure was changed to circular while crystalline BSTO films showed columnar structure. Due to insufficient annealing effect, amorphous BSTO phase was observed when the thickness of the amorphous layers exceeded 30 nm. Amorphous BSTO layer could also prevent the formation of oxygen deficient region in $RuO_2$ surface. Leakage current of total BSTO films decreased with increasing amorphous layer thickness due to structural modifications. Dielectric constant showed maxi-mum value of 343 when amorphous layer thickness was 30 nm at which the improvement by grain growth and the degradation by amorphous phase were balanced.

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Quantitative Analysis of Ultrathin SiO2 Interfacial Layer by AES Depth Profilitng

  • Soh, Ju-Won;Kim, Jong-Seok;Lee, Won-Jong
    • The Korean Journal of Ceramics
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    • 제1권1호
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    • pp.7-12
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    • 1995
  • When a $Ta_O_5$ dielectric film is deposited on a bare silicon, the growth of $SiO_2$ at the $Ta_O_5$/Si interface cannot be avoided. Even though the $SiO_2$ layer is ultrathin (a few nm), it has great effects on the electrical properties of the capacitor. The concentration depth profiles of the ultrathin interfacial $SiO_2$ and $SiO_2/Si_3N_4$ layers were obtained using an Auger electron spectroscopy (AES) equipped with a cylindrical mirror analyzer (CMA). These AES depth profiles were quantitatively analyzed by comparing with the theoretical depth profiles which were obtained by considering the inelastic mean free path of Auger electrons and the angular acceptance function of CMA. The direct measurement of the interfacial layer thicknesses by using a high resolution cross-sectional TEM confirmed the accuracy of the AES depth analysis. The $SiO_2/Si_3N_4$ double layers, which were not distinguishable from each other under the TEM observation, could be effectively analyzed by the AES depth profiling technique.

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Effect of annealing pressure on the growth and electrical properties of $YMnO_3$ thin films deposited by MOCVD

  • Shin, Woong-Chul;Park, Kyu-Jeong;Yoon, Soon-Gil
    • Journal of Korean Vacuum Science & Technology
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    • 제4권1호
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    • pp.6-10
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    • 2000
  • Ferroelectric YMnO$_3$ thin films were deposited on $Y_2$O$_3$/si(100) substrates by metalorganic chemical vapor deposition. The YMnO$_3$ thin films annealed in vacuum ambient (100 mTorr) above 75$0^{\circ}C$ show hexagonal structured YMnO$_3$. However, the film annealed in oxygen ambient shows poor crystallinity, and the second phase as $Y_2$O$_3$ and orthorhombic-YMnO$_3$ were shown. The annealing ambient and pressure on the crystallinity of YMnO$_3$ thin films is very important. The C-V characteristics have a hysteresis curve with a clockwise rotation, which indicates ferroelectric polarization switching behavior. When the gate voltage sweeps from +5 to 5 V, the memory window of the Pt/YMnO$_3$/Y$_2$O$_3$/Si gate capacitor annealed at 85$0^{\circ}C$ is 1.8 V. The typical leakage current densities of the films annealed in oxygen and vacuum ambient are about 10$^{-3}$ and 10$^{-7}$ A/cm$^2$ at applied voltage of 5 V.

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바이오칩 응용을 위한 저온 소결형 PZT 후막의 졸 코팅 재료와 횟수에 따른 물성 및 전기적 특성 (Properties and Electrical Characterization by Materials md the number of Times of Sol Coating of PBT Thick Film for Biochip)

  • 박재홍;손진호;김태송;황재섭;박형호;김환
    • 한국재료학회:학술대회논문집
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    • 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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    • pp.139-139
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    • 2003
  • 많은 압전 후막은 여러 감지소자, 통신 및 사무자동화 기기, 전기 및 전자부품, 의료장비 및 국방산업에 까지 널리 응용되어 왔다. 그 중에서도 압전특성이 뛰어난 PZT 후막은 마이크로 펌프, 밸브, 헤드, 모터, 트랜스듀서 뿐 아니라 최근 바이오칩용 센서와 액추에이터로서 널리 연구되고 있다. 또한 마이크로 센서와 액추에이터 의 제작 및 구동을 위한 MEMS 기술의 도입으로 실리콘 베이스의 소자 개발이 집중되고 있다. 스크린 프린팅 방법은수 마이크론에서 수십 마이크론 후막의 실현이 용이하고 비교적 경제적이며 소자신뢰도가 높고 대량생산에 유리하여 활발한 연구가 진행 중이다. 그러나 후막은 벌크에 비해 기공률이 높고, 또 소자응용에 있어서 고온소결 시 MEMS공정을 위한 실리콘 베이스 기판과의 확산 및 반응에 의 한 계면 및 활물질 성능의 저하가 문제가 되고 있다. 따라서 본 연구에서는 스크린 프린팅과 더불어 졸 코팅 방법의 도입으로 후막의 성형 및 소결 밀도를 높임과 동시에 여러 확산 방지 막의 증착으로 capacitor 형 PZT 후막의 물성 및 전기 적 특성을 향상시키고자 하였다.

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