• 한국세라믹학회지
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• 제31권11호
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• pp.1330-1336
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• 1994

Ta2O5 films were deposited on the p-Si(100) substrates by ECR-PECVD and annealed in O2 atmosphere. The thicknesses of Ta2O5/SiO2 layers were measured by an ellipsometer and a cross-sectional TEM. Annealing in O2 atmosphere enhanced the stoichiometry of the Ta2O5 film and reduced the impurity carbon content. Ta2O5 films were crystallized at the annealing temperatures above 75$0^{\circ}C$. The best leakage current characteristics and the maximum dielectric constant of Ta2O5/SiO2 film capacitor were observed in the specimen annealed at $700^{\circ}C$ and 75$0^{\circ}C$, respectively. The flat band voltage of the Al/Ta2O5/SiO2/p-Si MOS capacitor was varied in the range of -0.6~-1.6 V with the annealing temperature. The conduction mechanism in the Ta2O5 film, the variation of the effective oxide charge density with the annealing temperature, and the effective electric field distribution in the Ta2O5/SiO2 double layer were also discussed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.271-271
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• 2010

$BaTiO_3$(BT) has high permittivity so that has been applied to dielectric and insulator materials in 3D system-level package integration. In order to achieve excellent performance of device, the BT layer should be highly dense. In this study, BT thick films were prepared by the inkjet printing method. And these films were cured at $280^{\circ}C$ after infiltration of polymer resin. As a result, we have successfully fabricated not only the inkjet-printed hybrid BT film but also metal-insulator-metal(MIM) capacitor without sintering process. Changes in the dielectric constant of BT hybrid film with particle size and packing density were investigated. The dielectric constant was increased with increasing packing density and particle size. Further, the BT hybrid film using two different size particles had even higher packing density and dielectric constant.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.455-458
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• 2001

The thin films of high pemitivity in ferroelectric materials using a capacitor are applied to DRAMs and FRAMs. (Ba, Sr)$TiO_3$ thin films as ferroelectric materials were prepared by the sol-gel method and made by spin-coating on the Pt/Ti/$SiO_2/Si$ substrate at 4,000 [rpm] for 10 seconds. The devices of BST thin films to composite $(Ba_{0.7},Sr_{0.3})TiO_3$ were fabricated by changing of the depositing layer number on $Pt/Ti/SiO_2/Si$ substrate. The thin film capacitor to be ferroelectric devices was investigated by structural and electrical properties. The thickness of BST thin films at each coating numbers 3, 4 and 5 times was $2500[\AA]$, $3500[\AA]$, $3800[\AA]$. The dielectric factor of thin film when the coating numbers were 3, 4 and 5 times was 190, 400 and 460 on frequency l[MHz]. The dielectric loss of BST thin film was linearly increased by increasing of the specimen area.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.455-458
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• 2001

The thin films of high permitivity in ferroelectric materials using a capacitor are applied to DRAMs and FRAMs. (Ba, Sr)TiO$_3$ thin films as ferroelectric materials were prepared by the sol-gel method and made by spin-coating on the Pt/Ti/SiO$_2$/Si substrate at 4,700 [rpm] for 10 seconds. The devices of BST thin films to composite (Ba$\_$0.7/Sr$\_$0.3/)TiO$_3$ were fabricated by changing of the depositing layer number on Pt/Ti/SiO$_2$/Si substrate. The thin film capacitor to be ferroelectric devices was investigated by structural and electrical properties. The thickness of BST thin films at each coating numbers 3, 4 and 5 times was 2500[${\AA}$], 3500[${\AA}$], 3800[${\AA}$]. The dielectric factor of thin film when the coating numbers were 3, 4 and 5 times was 190, 400 and 460 on frequency 1[MHz]. The dielectric loss of BST thin film was linearly increased by increasing of the specimen area.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.66-66
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• 2007

Lead zirconate titanate (PZT) is one of the most attractive perovskite-type materials for ferroelectric random access memory (FRAM) due to its higher remanant polarization and the ability to withstand higher coercive fields. We first applied the damascene process using chemical mechanical polishing (CMP) to fabricate the PZT thin film capacitor to solve the problems of plasma etching including low etching profile and ion charging. The $0.8{\times}0.8\;{\mu}m$ square patterns of silicon dioxide on Pt/Ti/$SiO_2$/Si substrate were coated by sol-gel method with the precursor solution of PZT. Damascene process by CMP was performed to pattern the PZT thin film with the vertical sidewall and no plasma damage. The polarization-voltage (P-V) characteristics of PZT capacitors and the current-voltage characteristics (I-V) were examined by change of process parameters. To examine the CMP induced damage to PZT capacitor, the domain structure of the polished PZT thin film was also investigated by piezoresponse force microscopy (PFM).

• 한국전기전자재료학회논문지
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• 제14권12호
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• pp.1001-1007
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• 2001

In this study, high dielectric materials, (Pb,La)Ti $O_3$ thin films were fabricated by PLD (Pulsed Laser Deposition) method and investigated in terms of structural and electrical characteristics in order to develope the dielectric materials for the use of new capacitor layers of Giga bit-level DRAM. The deposition conditions were examined in order to fabricate uniform thin films through systematic changes of oxygen pressures and substrate temperature. The uniform thickness and smooth morphology of (P $b_{0.72}$L $a_{0.28}$)Ti $O_3$ thin films were obtained at the conditions of substrate-target distance 5.5[cm], laser energy density 2.1[J/$\textrm{cm}^2$], oxygen pressure 200[mTorr] and substrate temperature 500[$^{\circ}C$]. After the (P $b_{0.72}$L $a_{0.28}$)Ti $O_3$ thin films were fabricated under the above conditions, they were post-annealed by RTA process in order to increase the dielectric constant. The film thickness of 1200 [$\AA$] had dielectric constant 821. Assuming that operating voltage is 2V, leakage current density of (P $b_{0.72}$L $a_{0.28}$)Ti $O_3$ thin films would result into 10$^{-7}$ [A/$\textrm{cm}^2$] and satisfied the specification of 256M DRAM planar capacitor, 4$\times$10$^{-7}$ [A/$\textrm{cm}^2$]m}^2$]

• Journal of Electrical Engineering and Technology
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• 제13권2호
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• pp.677-687
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• 2018

This paper presents a novel power decoupling control scheme with the bidirectional buck-boost converter for primary-side regulation photovoltaic (PV) micro-inverter. With the proposed power decoupling control scheme, small-capacitance film capacitors are used to overcome the life-span and reliability limitations of the large-capacitance electrolytic capacitors. Then, an improved flyback PV inverter is employed in continuous conduction mode with primary-side regulation for the PV power conditioning. The proposed power-decoupling controller shares the reference for primary side current regulation of the flyback PV inverter. The decoupling controller shapes the input current of the bidirectional buck-boost converter. The shared reference eliminates the phase-delay between the input current to the bidirectional buck-boost converter and the double frequency current at the PV primary current. The elimination of the phase-delay in dynamic response enhances the ripple rejection capability of the power decoupling buck-boost converter even with small film capacitor. With proposed power decoupling control scheme, the additional advantage of the primary-side regulation of flyback PV inverter is that there is no need to have an extra current sensor for obtaining the ripplecurrent reference of the decoupling current-controller of the power-decoupling buck-boost converter. Therefore, the proposed power decoupling control scheme is cost-effective as well as the size benefit. A new transient analysis is carried out which includes the source voltage dynamics instead of considering the source voltage as a pure voltage source. For verification of the proposed control scheme, simulation and experimental results are presented.

• Transactions on Electrical and Electronic Materials
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• 제13권5호
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• pp.237-240
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• 2012

A conducting polymer, poly 3-hexylthiophene (P3HT) is characterized with the metal-insulator-semiconductor (MIS) measurement method and the high frequency planar circuit method. From the MIS measurement method, the relative dielectric constant of the P3HT film is estimated to be 4.4. For the high frequency planar circuit method, a coplanar waveguide is fabricated on the P3HT film. When applying +20 V to the CPW on P3HT film, the P3HT film is in accumulation mode and becomes lossy. The CPW on P3HT film is 1.5 dB lossier than the CPW on $SiO_2$ film without P3HT film at 50 GHz.

• 한국세라믹학회지
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• 제34권3호
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• pp.233-240
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• 1997

LCR(Inductor Capacitor Resistor) network을 구성하기 위한 90$0^{\circ}C$소성용 Ru계 저항체를 제조하였다. 이 90$0^{\circ}C$동시소성용 저항 페이스트는 유리상 조성중 용융온도를 낮춰주는 PbO의 양을 감소시키고 Al2O3와 SiO2의 양을 증가시켜 제조하였다. 본 연구에서는 Alumina기판 위에 인쇄하고 소결한 저항체의 면저항과 Inductor와 Capacitor기판을 사용하여 제조한 저항체의 면저항 및 기판과 저항체간의 계면에 대한 관찰하였다. 또한 RuO2의 양을 달리하여 제조한 저항체의 저항값 변화에 대해서도 고찰하였다. 동시소성으로 소결한 경우, Alumina기판에서는 103~106$\Omega$/$\square$의 저항값을 얻을 수 있었으나, Inductor와 Capacitor기판에서는 저항값의 측정 범위를 벗어났다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.8-9
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• 2006

Hafnium oxide ($HfO_2$) thin films were deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and $O_3$. Prior to the deposition of $HfO_2$ films, a thin Hf ($10\;{\AA}$) metal layer was deposited. Deposition temperature of $HfO_2$ thin film was $350^{\circ}C$ and its thickness was $150\;{\AA}$. Samples were then annealed using furnace heating to temperature ranges from 500 to $900^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Thermally evaporated $3000\;{\AA}$-thick AI was used as top electrode. In this work, We study the interface characterization of $HfO_2$/Hf/Si MOS capacitor depending on annealing temperature. Through AES(Auger Electron Spectroscopy), capacitance-voltage (C-V) and current-voltage (I-V) analysis, the role of Hf layer for the better $HfO_2$/Si interface property was investigated. We found that Hf meta1 layer in our structure effective1y suppressed the generation of interfacial $SiO_2$ layer between $HfO_2$ film and silicon substrate.