• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.461-462
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• 2005

In order to improve the efficiency of dye-sensitized solar cell (DSC), $TiO_2$ electrode screen-printed on transparent conducting oxide (TCO) substrate was sintered in variation with different temperature(350 to $550^{\circ}C$). $TiO_2$ electrode on fluorine doped tin oxide (FTO) glass was assembled with Pt counter electrode on FTO glass. I-V properties of DSC were measured under solar simulator. Also, effect of sintering temperature on surface morphology of $TiO_2$ films was investigated to understand correlation between its surface morphology and sintering temperature. Such surface morphology was observed by atomic force microscopy (AFM). From the measurement results, at sintering temperature of $500^{\circ}C$, both efficiency and fill factor of DSC were mutually complementary, enhancing highest fill factor and efficiency. Consequently, it was considered that optimum sintering temperature of $\alpha$-terpinol included $TiO_2$ paste is at $500^{\circ}C$.

• Journal of the Korean Vacuum Society
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• v.20 no.3
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• pp.189-194
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• 2011

Si-cell was prepared with various types owing to the etching times textured by the KOH etching solution. The pn junction for solar cell was prepared on p-type Si wafer by the furnace using the $POCl_3$ and oxygen mixed precursor, and the metalization was done using by the Al back electrode and Ag front electrode. Textured Si surface was etched by the pyramid formation. The efficiency and the fill factor was increased in the Si-cell with a large size of pyramids, because of the series resistances decrease depending on the increasing of the photon absorbance. Increasing of the absorbance occurred the induction of the short current and open voltage, and then the efficiency was increased.

• 한국신재생에너지학회:학술대회논문집
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• 2006.06a
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• pp.199-201
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• 2006

A lot of researches and experiments have been performed to make more efficient dye-sensitized solar cell. Among them, insertion of a grid electrode in DSC is one method to increase overall performance as being shortened distance of electrons' movement by diffusion. In this paper, we measured overall characteristics which is included voltage-current characteristic curve, efficiency, fill factor by comparison between DSC without and with grid electrode. As a result, we got maximum 1.8 times increase of efficiency and approximately 1.7 times rise of fill factor. And we experimented 8, 10, 12, 14mm of grid gap and compared their results to optimize grid gap which is able to incite the most effective movement of electrons. Consequently, we got the result that electrons' movement is the most effect ive when grid gap is approximately 12mm.

• 한국신재생에너지학회:학술대회논문집
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• 2006.06a
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• pp.158-161
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• 2006

Superstrate pin amorphous silicon thin-film (a-Si:H) solar cells are prepared on $SnO_2:F$ and ZnO:Al transparent conducting oxides (TCO) In order to see the effect of TCO/P-layers on a-Si:H solar cell operation. The solar cells prepared on textured ZnO:Al have higher open circuit voltage $V_{oc}$ than cells prepared on $SnO_2:F$. Presence of thin microcrystalline p-type silicon layer $({\mu}c-Si:H)$ between ZnO:Al and p a-SiC:H plays a major role by causing improvement in fill factor as well as $V_{oc}$, of a-Si:H solar cells prepared on ZnO:Al TCO. Without any treatment of pi interface, we could obtain high $V_{oc}$, of 994mv while keeping fill factor (72.7%) and short circuit current density $J_{sc}$ at the same level as for the cells on $SnO_2:F$ TCO. This high $V_{oc}$ value can be attributed to modification in the current transport in this region due to creation of a potential barrier.

• Journal of the Semiconductor & Display Technology
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• v.8 no.2
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• pp.59-62
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• 2009

In order to check the validation of LC simulation, 0.7 inch LCOS panel in full-HD resolution was fabricated and used for the electro-optical measurement. Compared the measured data with the calculated data, the averaged difference was 1.72% under 0 ~ +6 V bias on pixel electrode. To improve the optical characteristics of full-HD LCOS panel, the planar structure and trench structures (0.1 um, 0.2 um and 0.3 um-in-depth) between adjacent pixels were investigated with LC simulation. The planar structure showed the higher reflectance and faster reflectance-voltage response time than the trench structure. The optical fill factor and contrast ratio of planar structure were also higher than those of trench structures. As compared 1 um-in-depth trench structure resembled to the real structure with the planar structure, the optical fill factor was improved by 1.15% and the contrast ratio was improved by 5.26%. In order to minimize the loss of luminance and contrast ratio, the planar structure need to be applied between adjacent pixels.

• East Asian Economic Review
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• v.18 no.2
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• pp.111-142
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• 2014

We examine whether country fundamentals help explain the cross-section of currency excess returns. For this purpose, we consider fundamental variables such as default risk, foreign exchange rate regime, capital control as well as interest rate in the multi-factor model framework. Our empirical results show that fundamental factors explain a large part of the cross-section of currency excess returns. The zero-intercept restriction of the factor model is not rejected for most currencies. They also reveal that our factor model with country fundamentals performs better than a factor model with usual investment-style factors. Our main empirical results are based on 2001-2010 balanced panel data of 19 major currencies. This paper may fill the gap between country fundamentals and practitioners' strategies on currency investment.

• Proceedings of the KIEE Conference
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• 1997.07f
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• pp.2002-2006
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• 1997

A new PF correction topology, Improved Valley Fill (IVF) with Valley Boost Converter (VBC) used in the electronic ballast for fluorescent lamp is presented. The IVF can adjust the valley voltage higher than half the peak line voltage. Hence, there is no pulsating line current around the line voltage peak, PF and THD are significantly improved. The VBC is added to the IVF to achieve unity PF and to increase the valley voltage. The measured PF and THD for a prototype electronic ballast are 0.997 and 5%, respectively, and the lamp current CF is as low as 1.5

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2798-2800
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• 1999

A new circuit, modified valley fill (MVF) combined with resonant inductor of the self-excited resonant inverter and charge pump capacitors(CPCs), is presented to achieve high PF electronic ballast providing sufficient preheat current to lamp filaments for soft start maintaining low DC bus voltage. The MVF can adjust the valley voltage higher than half the peak line voltage. The CPCs draw the current from the input line to make up the current waveform during the valley interval. The measured PF and THD are 0.99 and 12%, respectively. The lamp current CF is also acceptable in the proposed circuit. The proposed circuit is suitable for implementing cost-effective electronic ballast.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.4
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• pp.297-302
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• 2014

In this paper, a LED driver compatible with TRIAC-dimmer applying active bleeder is proposed. If TRIAC-dimmer is connected with LED driver, flicker phenomenon occurs by TRIAC malfunction. In order to prevent this problem, a current over holding current must flow into TRIAC. Therefore, additional circuit compatible with TRIAC-dimmer is required to provide enough current. Passive bleeder has power loss in whole operation period. The proposed circuit apply a valley-fill circuit for power-factor-correction and a novel active bleeder detecting malfunction point of TRIAC. Therefore, it prevent malfunction of TRIAC-dimmer and have advantage of higher efficiency than passive bleeder. To verify the validity of proposed circuit, 13W-lighting LED driver prototype has been proposed.

• Journal of Energy Engineering
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• v.21 no.3
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• pp.243-248
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• 2012

In this study, The report analysed the characteristics of power drop and damage of surface in solar cell through high temperature and humidity test. The solar cells were tested during the 1000hr in $85^{\circ}C$ temperature and 85% humidity conditions, that excerpted standard of PV Module(KS C IEC-61215). An analysis of the cell surface through EL(Electroluminescence), the cell has partly change of surface in yearly. Single-crystalline Solar cell efficiency is decreased from 17.7% to 15.6% and decreasing rate is 11.9%. On the other hand, Poly-crystalline Solar cell efficiency is decreased from 15.5% to 14.0% and decreasing rate is 9.3%. A comparison of the fill factor for analysis of electro characteristic in yearly, Single-crystalline Solar cell efficiency is decreased from 78.7% to 78.1% and decreasing rate is 4.7%. On the other hand, Poly-crystalline Solar cell efficiency is decreased from 78.1% to 76.7% and decreasing rate is 1.8%. Single-crystalline has more bigger power drop than poly-crystalline by the silicon purity and silicon atom arrangement. Also, FF decreasing rate has more bigger drop than efficiency decreasing rate for the reason that the damage of surface by exterior environmental factor is the more influence in cell than other reason that is decreasing FF by damage of p-n junction.