• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.80-80
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• 2009

Recently, multiferroics have attracted much attention due to their numorous potentials. In this work, we attemped to utilize the multiferroics as an alternative material for ferroelectrics. Ferroelectric materials have been stadied to ferroelectric random access memories, however, some inevitable problems prevent it from inplementation. multiferroics shows a ferroelectricity and has low process temperature $BiFeO_3$(BFO) films have good ferroelectric properties but poor leakage characterization. Thus we tried, in this work, to adopt $HfO_2$ insulating layer for metal-ferroelectric-insulator-semiconductor(MFMIS) structure to surpress to leakage current. $BiFeO_3$(BFO) thin films were fabricared by using a sol-gel method on $HfO_2/Si$ structure. Ferroelectric BFO films on a p-type Si(100)wafer with a $HfO_2$ buffer layer have been fabricated to form a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The $HfO_2$ insulator were deposited by using a sol-gel method. Then, they were carried out a rapid thermal annealing(RTA) furnace at $750\;^{\circ}C$ for 10 min in $N_2$. BFO films on the $HfO_2/Si$ structures were deposited by sol-gel method and they were crystallized rapid thermal annealing in $N_2$ atomsphere at $550\;^{\circ}C$ for 5 min. They were characterized by atomic force microscopy(AFM) and Capacitance-voltage(C-V) curve.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2007년도 The 1st International Symposium on Advanced Magnetic Materials
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• pp.306.1-306.1
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• 2007

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.319-322
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• 2003

To match the charge induced by the insulators $CeO_2$ with the remanent polarization of ferro electric SBT thin films, areas of Pt/SBT/Pt (MFM) and those of $Pt/CeO_2/Si$ (MIS) capacitors were ind ependently designed. The area $S_M$ of MIS capacitors to the area $S_F$ of MFM capacitors were varied from 1 to 10, 15, and 20. Top electrode Pt and SBT layers were etched with for various area ratios of $S_M\;/\;S_F$. Bottom electrode Pt and $CeO_2$ layers were respectively deposited by do and rf sputtering in-situ process. SBT thin film were prepared by the metal orgnic decomposition (MOD) technique. $Pt(100nm)/SBT(350nm)/Pt(300nm)/CeO_2(40nm)/p-Si$ (MFMIS) gate structures have been fabricated with the various $S_M\;/\;S_F$ ratios using inductively coupled plasma reactive ion etching (ICP-RIE). The leakage current density of MFMIS gate structures were improved to $6.32{\times}10^{-7}\;A/cm^2$ at the applied gate voltage of 10 V. It is shown that in the memory window increase with the area ratio $S_M\;/\;S_F$ of the MFMIS structures and a larger memory window of 3 V can be obtained for a voltage sweep of ${\pm}9\;V$ for MFMIS structures with an area ratio $S_M\;/\;S_F\;=\;6$ than that of 0.9 V of MFS at the same applied voltage. The maximum memory windows of MFMIS structures were 2.28 V, 3.35 V, and 3.7 V with the are a ratios 1, 2, and 6 at the applied gate voltage of 11 V, respectively. It is concluded that ferroelectric gate capacitors of MFMIS are good candidates for nondestructive readout-nonvolatile memories.

• 한국재료학회지
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• 제11권5호
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• pp.367-371
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• 2001

RF magnetron sputtering 법으로 T $a_2$ $O_{5}$ 세라믹 타겟과 S $r_2$N $b_2$ $O_{7}$ 세라믹 타겟을 동시 sputtering하여 저유전율 S $r_2$(T $a_{1-x}$ , N $b_{x}$)$_2$ $O_{7}$(STNO) 박막을 p-type Si (100) 기판 위에 증착하여 NDRO 강유전체 메모리 (Non-destructive read out ferro-electric random access memory)에 사용되는 Pt/STNO/Si (MFS) 구조의 응용 가능성을 확인하였다. Sr$_2$Nb$_2$ $O_{7} (SN O)$ 타겟과 T $a_2$ $O_{5}$ 타겟의 출력의 비를 100w/100w, 70w/100w, 그리고 50w/100w로 조절하면서 x 값을 달리하여 조성을 변화시켰다. 성장된 박막을 8$50^{\circ}C$, 90$0^{\circ}C$, 그리고 9$50^{\circ}C$에서 1시간 동안 산소 분위기에서 열처리하였다. 조성과 열처리 온도에 따른 구조적 특징을 XRD에 의해 관찰하였으며 표면특성은 FE-SBM에 의해 관찰하였고, C-V 측정과 I-V 측정으로 박막의 전기적 특성을 조사하였다. SNO 타겟과 T $a_2$ $O_{5}$ 타켓의 출력비에 따른 STNO 박막의 성장 결과 70W/170W의 출력비에서 성장된 STNO박막에서 Ta의 양이 상대적 맡은 x=0.4였으며 가장 우수한 C-V 특성 및 누설 전류 특성을 보였다. 이 조성에서 성장된 STNO박막은 3-9V외 인가전압에서 메모리 윈도우 갑이 0.5-8.3V였고 누설전류밀도는 -6V의 인가전압에서 7.9$\times$10$_{-8}$A /$\textrm{cm}^2$였다.