• ETRI Journal
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• v.33 no.1
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• pp.50-59
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• 2011

In the current very deep submicron technology era, fault tolerant mechanisms perform an essential function to cope with the effects of soft errors. To evaluate the effectiveness of the fault tolerant mechanism, reliability engineers use simulated fault injections using either saboteur modules or mutants in the simulation model. However, the two methods suffer from both inefficiency in the simulation mechanism and difficulties with the experimental setups. To overcome these inefficiencies, we propose the Verilog-based simulated fault injection (VFI) technique. VFI has the following advantages. First, modification of the design model is unnecessary. Second, the fault injection simulation procedure is simple and efficient. Third, various types of fault injection experiments can be performed. To evaluate the effectiveness of the proposed methodology, we developed a VFI environment using the ICARUS Verilog Simulator. From the experimental results, we were able to qualitatively evaluate the reliability of the target simulation models and to assess the effectiveness of the employed fault-tolerance mechanisms.

• The KIPS Transactions:PartA
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• v.16A no.4
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• pp.235-244
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• 2009

The mission-critical computer for air defense has to maintain its operation without any fault for a long mission time and is required to implement at low cost. Now the reliability of the mission critical-computer using Active Sparing Redundancy fault-tolerant technique is inferior to that of the computer using TMR technique. So in this paper are proposed Extended ASR(EASR) technique that provides higher reliability than that of the computer using TMR technique. The fault-tolerant performance of the implemented mission-critical computer is proven through reliability analysis and numbers of fault recovery test. Also, the reliability of the mission-critical computer using EASR technique is compared with those of computer using ASR and TMR techniques. EASR technique is very suitable to the mission-critical computer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.307-311
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• 2015

In this paper, we propose an efficient fault-recovery technique for CGRA (Coarse-Grained Reconfigurable Architecture) based multi-core architecture. The proposed technique is intra/inter-CGRA co-reconfiguration technique based on a ring-based sharing fabric (RSF) and it enables exploiting the inherent redundancy and reconfigurability of the multi-CGRA for fault-recovery. Experimental results show that the proposed approaches achieve up to 73% fault recoverability when compared with completely connected fabric (CCF).

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.615-628
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• 2015

CGRA (Coarse-Grained Reconfigurable Architecture) based multi-core architecture can be considered as a suitable solution for the fault-tolerant computing. However, there have been a few research projects based on fault-tolerant CGRA without exploiting the strengths of CGRA as well as their works are limited to single CGRA. Therefore, in this paper, we propose two approaches to enable exploiting the inherent redundancy and reconfigurability of the multi-CGRA for fault-recovery. One is a resilient inter-CGRA fabric that is ring-based sharing fabric (RSF) with minimal interconnection overhead. Another is a novel intra/inter-CGRA reconfiguration technique on RSF for maximizing utilization of the resources when faults occur. Experimental results show that the proposed approaches achieve up to 94% faulty recoverability with reducing area/delay/power by up to 15%/28.6%/31% when compared with completely connected fabric (CCF).

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1073-1081
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• 2000

This paper proposes a new fault-tolerant technique for bitonic sorting networks which can be used for designing ATM switches based on Batcher-Banyan network. The main goal in this paper is to design a cost-effective fault-tolerant bitonic sorting network. In order to recover a fault, additional comparison elements and additional links are used. A Dynamic Redundant Bitonic Sorting (DRBS) network is based on the Dynamic Redundant network and can be constructed with several different variations. The proposed fault-tolerant sorting network offers high fault-tolerance; low time delays; maintenance of cell sequence; simple routing; and regularity and modularity.

• Journal of Electrical Engineering and Technology
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• v.13 no.4
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• pp.1740-1751
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• 2018

This paper proposes a novel fault tolerant tracking control (FTTC) scheme for a class of nonlinear systems with actuator failures based on the policy iteration (PI) algorithm and the adaptive fault observer. The estimated actuator failure from an adaptive fault observer is utilized to construct an improved performance index function that reflects the failure, regulation and control simultaneously. With the help of the proper performance index function, the FTTC problem can be transformed into an optimal control problem. The fault tolerant tracking controller is composed of the desired controller and the approximated optimal feedback one. The desired controller is developed to maintain the desired tracking performance at the steady-state, and the approximated optimal feedback controller is designed to stabilize the tracking error dynamics in an optimal manner. By establishing a critic neural network, the PI algorithm is utilized to solve the Hamilton-Jacobi-Bellman equation, and then the approximated optimal feedback controller can be derived. Based on Lyapunov technique, the uniform ultimate boundedness of the closed-loop system is proven. The proposed FTTC scheme is applied to reconfigurable manipulators with two degree of freedoms in order to test the effectiveness via numerical simulation.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1371-1373
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• 2005

Nowadays, Intelligent Electronic Devices(IED) are widely used in power system. In order to improve the selectivity, sensitivity, and reliability of the power system composed by IEDs, A new fault tolerant IED system based on agent technique is presented in this paper. in the presented system, different with existing IED systems, the redundancies are drawn out from IED devices, and compose a standby backup system. And those redundancies are not specified to a particular type of IEDs. By using the agent technique, redundancies can download agents to modify their functions to fit different types of IEDs. As a conclusion, the reliability of the presented system is estimated in this paper.

• The KIPS Transactions:PartA
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• v.15A no.6
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• pp.309-316
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• 2008

The mission-critical engagement control computer for air defense has to maintain its operation without any fault for a long mission time. The mission performed by large-scale and complex embedded software is extremely critical in terms of dependability and safety of computer system, and it is very important that engagement control computer has high reliability. The engagement control computer was implemented using four processors. The distributed computer composed of four processors quarantees the dependability and safety, and ASR fault-tolerant technique applied to each processor guarantees the reliability. In this paper, the mechanism and performance of ASR fault-tolerant technique are analysed. And MTBF, reliability, availability, and cost-effectiveness for ASR, DMR and TMR techniques applied to the engagement control computer are analysed. The mission-critical engagement control computer using software-based ASR fault-tolerant technique provides high reliability and fast recovery time at a low cost. The mission reliability of the engagement control computer using ASR technique in 4 processors board is almost same the reliability of the computer using TMR technique in 6 processors board. ASR technique is most suitable to the mission-critical engagement control computer.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.37 no.5
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• pp.464-469
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• 2009

In this study, a new fault tolerant controller based on a model following adaptive technique is applied to the reconfiguration mode of supersonic advanced trainer. The designed controller is applied to the flight control system of high performance aircraft. To verify the performance of the proposed controller, numerical simulations are executed using a non-realtime nonlinear verification tool.

• The Transactions of the Korea Information Processing Society
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• v.5 no.12
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• pp.3088-3098
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• 1998

The arrangement graph, which is a viable interconnection scheme for parallel and distributed systems, has been proposed as an attactive altemative to the n-cube. However, A fault tolerant design model which is well suitable for the arrangement graph doesn't has been proposd until recently, but fault tolerant design modelsfor many schemes have been proposed ina large number of paper. So, our paper presents a new fault tolerant design technique suited for the arrangement graph. To maintains the previous structures when it ocurs a fault in the current processing, the scheme properly sugbstitutes a fault-componnent into the existing structures by adding a spare component. the first of all, it converts arrangement graph into a circulant graph using the hamiltonian property and then uses automorphism of circulant graph to tolerate faults. Also, We optimize the cost of rate fault tolerant architectures by adding exactly k spare processor while tolerating up to k processor and minimizing the maximum number of limks per processor. Specially, we proposes a new techniue to minimize the maximum number of links.