• 제목/요약/키워드: Fault-Tolerant Design

검색결과 196건 처리시간 0.036초

일반적 네트워크에서의 결함허용 시스템 구성 알고리즘에 관한 연구 (A Study on Fault-Tolerant System Construction Algorithm in General Network)

  • 문윤호;김병기
    • 한국통신학회논문지
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    • 제23권6호
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    • pp.1538-1545
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    • 1998
  • 시스템의 신뢰성은 디지털 컴퓨터 시대가 시작된 이래 가장 중요한 관심사가 되어 왔다. 신뢰성을 증가시키는 가장 최근 방법 중 하나는 결함허용 시스템을 고안하는 것이다. 본 논문에서는 일반적 그래프 형태에 대해 결함 허용 시스템의 구성방법을 제안하였다. 이 시스템은 여러 개의 예비 노드를 가진다. 최근까지 결함허용 시스템 고안은 루프 형태와 트리 형태의 네트워크에서만 작용되어 왔다. 그러나 그것들은 매우 제한적인 경우이다. 본문의 알고리즘은 그러한 많은 제약을 가지지 않고서 어느 유형이든 적용될 수 있는 융통성을 갖도록 시도되었다. 이 알고리즘은 여러 단계로 구성되는데 최소 직경 스패닝 트리의 검출 단계, 최적 노드 결정 단계, 원래의 연결성 복구 단계 및 최종적으로 중복 그래프의 구성 단계이다.

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가상화 기술을 이용한 임베디드 시스템상의 고장감내 PSTR 설계 (The Design of Fault Tolerant PSTR Using Virtualization Techniques on the Embedded System)

  • 유진호;한규종
    • 정보처리학회논문지:컴퓨터 및 통신 시스템
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    • 제3권12호
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    • pp.443-448
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    • 2014
  • 본 논문은 가상화 기술을 이용하여 PSTR에 기반한 고장감내 설계에 관련한 연구이다. 고장감내 PSTR 모델을 가상화 기술에 기반하여 구현하게 되면 프라이머리와 쉐도우 간의 통신성능이 향상되고 각 프라이머리와 쉐도우 내의 동작에 대한 모니터링이 용이하게 된다. 기존의 PSTR 모델은 프라이머리 하드웨어와 쉐도우 하드웨어 구성을 전제로 하여 프라이머리에서 본 임무를 수행하고 쉐도우에서는 프라이머리에서 고장이 발생했을 경우 취해야 할 동작을 준비하게 된다. 쉐도우에서 이러한 동작을 준비하므로 임무에 차질이 없도록 프라이머리는 다시 주 임무를 수행할 수 있게 된다. 본 논문에서는 임베디드 환경에서 고장감내 PSTR 모델을 가상화 기술을 이용하여 구현한다.

PDSO tuning of PFC-SAC fault tolerant flight control system

  • Alaimo, Andrea;Esposito, Antonio;Orlando, Calogero
    • Advances in aircraft and spacecraft science
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    • 제6권5호
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    • pp.349-369
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    • 2019
  • In the design of flight control systems there are issues that deserve special consideration and attention such as external perturbations or systems failures. A Simple Adaptive Controller (SAC) that does not require a-priori knowledge of the faults is proposed in this paper with the aim of realizing a fault tolerant flight control system capable of leading the pitch motion of an aircraft. The main condition for obtaining a stable adaptive controller is the passivity of the plant; however, since real systems generally do not satisfy such requirement, a properly defined Parallel Feedforward Compensator (PFC) is used to let the augmented system meet the passivity condition. The design approach used in this paper to synthesize the PFC and to tune the invariant gains of the SAC is the Population Decline Swarm Optimization ($P_DSO$). It is a modification of the Particle Swarm Optimization (PSO) technique that takes into account a decline demographic model to speed up the optimization procedure. Tuning and flight mechanics results are presented to show both the effectiveness of the proposed $P_DSO$ and the fault tolerant capability of the proposed scheme to control the aircraft pitch motion even in presence of elevator failures.

터보분자펌프용 고장허용 자기베어링 시스템 설계 및 개발 (Design and Implementation of a Fault-Tolerant Magnetic Bearing System For Turbo-Molecular Vacuum Pump)

  • 조성락;노명규;박병철
    • 대한기계학회:학술대회논문집
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    • 대한기계학회 2004년도 추계학술대회
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    • pp.760-765
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    • 2004
  • One of the obstacles for a magnetic bearing to be used in the wide range of industrial applications is the failure modes associated with magnetic bearings, which we don't expect for conventional passive bearings. These failure modes include electric power outage, power amplifier faults, position sensor faults, and the malfunction of controllers. Fault-tolerant magnetic bearing systems have been proposed so that the system can operate in spite of some faults in the system. In this paper, we designed and implemented a fault-tolerant magnetic bearing system for a turbo-molecular vacuum pump. The system can cope with the actuator/amplifier faults as well as the faults in position sensors, which are the two major fault modes in a magnetic bearing system.

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ATM 교환을 위한 비용 효율적인 동적 결함내성 bitonic sorting network (A Cost-Effective Dynamic Redundant Bitonic Sorting Network for ATM Switching)

  • 이재동;김재홍;최홍인
    • 한국정보처리학회논문지
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    • 제7권4호
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    • pp.1073-1081
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    • 2000
  • This paper proposes a new fault-tolerant technique for bitonic sorting networks which can be used for designing ATM switches based on Batcher-Banyan network. The main goal in this paper is to design a cost-effective fault-tolerant bitonic sorting network. In order to recover a fault, additional comparison elements and additional links are used. A Dynamic Redundant Bitonic Sorting (DRBS) network is based on the Dynamic Redundant network and can be constructed with several different variations. The proposed fault-tolerant sorting network offers high fault-tolerance; low time delays; maintenance of cell sequence; simple routing; and regularity and modularity.

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육각 보행 로봇의 내고장성 세다리 걸음새 (Fault-Tolerant Tripod Gaits for Hexapod Robots)

  • 양정민;노지명
    • 대한전기학회논문지:시스템및제어부문D
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    • 제52권12호
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    • pp.689-695
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    • 2003
  • Fault-tolerance is an important design criterion for robotic systems operating in hazardous or remote environments. This paper addresses the issue of tolerating a locked joint failure in gait planning for hexapod walking machines which have symmetric structures and legs in the form of an articulated arm with three revolute joints. A locked joint failure is one for which a joint cannot move and is locked in place. If a failed joint is locked, the workspace of the resulting leg is constrained, but hexapod walking machines have the ability to continue static walking. A strategy of fault-tolerant tripod gait is proposed and, as a specific form, a periodic tripod gait is presented in which hexapod walking machines have the maximum stride length after a locked failure. The adjustment procedure from a normal gait to the proposed fault-tolerant gait is shown to demonstrate the applicability of the proposed scheme.

여분을 갖는 시스템의 시리얼데이터통신 중재모듈의 개발 (A Development for Serial Data Communication Arbitration Module in Redundant System)

  • 신덕호;이종우;황종규;정의진;김종기
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 2002년도 춘계학술대회 논문집
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    • pp.530-534
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    • 2002
  • This paper show serial communication method in order to design how to interface between fault tolerant systems with redundancy. Problem has been in the method that fault tolerant system had switched of serial data with common switching device. This problem degrade reliability in itself and total system which is interfaced with that serial communication system. So Arbitration module of serial communication which is suggested in this paper can improve the reliability using voter algorithm which fault is detected passively.

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Fault Tolerance Design for Servo Manipulator System Operating in a Hot Cell

  • Jin, Jae-Hyun;Ahn, Sung-Ho;Park, Byung-Suk;Yoon, Ji-Sup;Jung, Jae-Hoo
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2003년도 ICCAS
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    • pp.2467-2470
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    • 2003
  • In this paper, fault tolerant mechanisms are presented for a servo manipulator system designed to operate in a hot cell. A hot cell is a sealed and shielded room to handle radioactive materials, and it is dangerous for people to work in the hot cell. So, remote operations are necessary to handle radioactive materials in the hot cell. KAERI has developed a servo manipulator system to perform such remote operations. However, since electric components such as servo motors are weak to radiations, fault tolerant mechanisms have to be considered. For fault tolerance of the servo manipulator system, hardware and software redundancy have been considered. In case of hardware, radioactive resistant electric components such as cables and connectors have been adopted and motors driving a transport have been duplicated. In case of software, a reconfiguration algorithm accommodating one motor's failure has been developed. The algorithm uses redundant axis to recover the end effector's motion in spite of one motor's failure.

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자체시험 (Self-Testing) 특성 비교기(Comparator)설계와 응용에 관한 연구 (A Study for Design and Application of Self-Testing Comparator)

  • 정용운;김현기;양성현;이기서
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 1998년도 창립기념 춘계학술대회 논문집
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    • pp.408-418
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    • 1998
  • This paper presents the implementation of comparator which is self-testing with respect to the faults caused by any single physical defect likely to occur in NMOS and CMOS integrated circuit. The goal is to use it for the fault-tolerant system. First, a new fault model for PLA(Programmable Logic Array) is presented. This model reflects several physical defects in VLSI circuits. It focuses on the designs based on PLA because VLSI chips are far too complex to allow detailed analysis of all the possible physical defects that can occur and of the effects on the operation of the circuit. Second, this paper shows that these design, which has been implemented with 2 level AND-ORor NOR-NOR circuit, are optimal in term of size. And it also presents a formal proof that a comparator implemented using NOR-NOR PLA, based on these design, is sol f-testing with respect to most single faults in the presented fault model. Finally, it discusses the application of the self-testing comparator as a building block for the implementation of the fault-tolerant system.

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Fault Tolerant Actuator for Steer-By-Wire Application

  • Mutschler P.;Krautstrunk A.
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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    • pp.741-745
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    • 2001
  • Reliability and safety of steer-by-wire concepts can be achieved by redundant designs. This paper discusses the design of a fault tolerant concept for a force feedback actuator with a standard three-phase PMSM. In contrast to usual drives, the phases of the machine are separated electrically. This design allows driving the machine with two instead of three phases in case of a fault. A superimposed torque controller adjusts the influence of fault currents and torque harmonics in two-phase operation and guarantees smooth torque at the steering wheel

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