• Journal of KIISE:Computer Systems and Theory
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• v.26 no.1
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• pp.33-42
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• 1999

지금까지의 bitonic sorting 에 대한 연구는 N 개의 key를 정렬하기 위해서는 N/2(or N)개의 프로세서가 필요하였다. 여기서는 프로세서의 수가 정렬하고자 하는 key 수에 독립적이고 또한 N/2개 이하인 경우를 고려하였다. 따라서 본 연구에서는 공유 메모리 병렬 컴퓨터 환경에서 N 개의 Key를 고정도니 수의 프로세서를 사용하여 O(log2N) 시간에 정렬 할 수 있는 두 종류의 범용 bitonic sorting 알고리즘을 구현하였다. 첫째로, VITURAL-GPBS 알고리즘은 하나의 프로세서를 사용하여 여러 개의 프로세서가 하는 역할을 모방하므로써 정렬을 수행하도록 하였다. 둘째로, VIRTUAL-GPBS 알고리즘보다 좀 더 효율적이고 빠른 FAST-GPBS 알고리즘을 소개하였다. 두 알고리즘의 주요 차이점은 FAST-GPBS 알고리즘에서는 각각의 프로세서에 배정된 여러 개의 key를 각 프로세서 내에서 가장 빠른 순차 정렬 알고리즘을 사용하면서 먼저 지역적으로 정렬을 함으로써 VIRTUAL-GPBS 보다 효율이 50% 이상 향상된 정렬을 수행할 수 있도록 하였다. FAST-GPBS 알고리즘은 compare-exchange 대신 merge-split 작업을 함으로써 컴퓨터의 사용 효율을 향상시킬 수 있다.

• Journal of Power Electronics
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• v.17 no.2
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• pp.346-357
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• 2017

The Modular Multilevel Converter (MMC) is particularly attractive for medium and high power applications such as High-Voltage Direct Current (HVDC) systems. In order to reach a high voltage, the number of cascaded submodules (SMs) is generally very large. Thus, in the applications with hundreds or even thousands of SMs such as MMC-HVDCs, the sorting algorithm of the conventional voltage balancing strategy is extremely slow. This complicates the controller design and increases the hardware cost tremendously. This paper presents a Two-Way Merge Sort (TWMS) strategy based on the prediction of the capacitor voltages under ideal conditions. It also proposes an innovative Insertion Sort Correction for the TWMS (ISC-TWMS) to solve issues in practical engineering under non-ideal conditions. The proposed sorting methods are combined with the features of the MMC-HVDC control strategy, which significantly accelerates the sorting process and reduces the implementation efforts. In comparison with the commonly used quicksort algorithm, it saves at least two-thirds of the sorting execution time in one arm with 100 SMs, and saves more with a higher number of SMs. A 501-level MMC-HVDC simulation model in PSCAD/EMTDC has been built to verify the validity of the proposed strategies. The fast speed and high efficiency of the algorithms are demonstrated by experiments with a DSP controller (TMS320F28335).

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.6
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• pp.2240-2254
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• 2021

We investigate the channel allocation problem in an ultra-dense device-to-device (D2D) enabled cellular network in underlaying mode where multiple D2D users are forced to share the same channel. Two kinds of low complexity solutions, which just require partial channel state information (CSI) exchange, are devised to resolve the combinatorial optimization problem with the quality of service (QoS) guaranteeing. We begin by sorting the cellular users equipment (CUEs) links in sequence in a matric of interference tolerance for ensuring the SINR requirement. Moreover, the interference quota of CUEs is regarded as one kind of communication resource. Multiple D2D candidates compete for the interference quota to establish spectrum sharing links. Then base station calculates the occupation of interference quota by D2D users with partial CSI such as the interference channel gain of D2D users and the channel gain of D2D themselves, and carries out the channel allocation by setting different access priorities distribution. In this paper, we proposed two novel fast matching algorithms utilize partial information rather than global CSI exchanging, which reduce the computation complexity. Numerical results reveal that, our proposed algorithms achieve outstanding performance than the contrast algorithms including Hungarian algorithm in terms of throughput, fairness and access rate. Specifically, the performance of our proposed channel allocation algorithm is more superior in ultra-dense D2D scenarios.

• The Transactions of the Korea Information Processing Society
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• v.2 no.3
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• pp.433-442
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• 1995

This paper presents an improved VLSI implementation of a parallel sorter to achieve O(Ν) time complexity. Many fast VLSI sort algorithms have been proposed for sorting N elements in O(log Ν) time. However, most such algorithms proposed have complex network structure without considering data input and output time. They are also very difficult to expand or to use in real applications. After analyzing the chip area and time complexity of several parallel sort algorithms with overlapping data input and output time, the most effective algorithm, the rebound sort algorithm, is implemented in VLSI with some improvements. To achieve O(Ν) time complexity, an improved rebound sorter is able to sort 8 16-bits records on a chip. And it is possible to sort more than 8 records by connecting chips in a chain vertically.

• Earthquakes and Structures
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• v.11 no.2
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• pp.347-369
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• 2016

The main objective of this paper is the robust multi-objective optimization design of semi-active tuned mass damper (STMD) system using genetic algorithms and fuzzy logic. For optimal design of this system, it is required that the uncertainties which may exist in the system be taken into account. This consideration is performed through the robust design optimization (RDO) procedure. To evaluate the optimal values of the design parameters, three non-commensurable objective functions namely: normalized values of the maximum displacement, velocity, and acceleration of each story level are considered to minimize simultaneously. For this purpose, a fast and elitist non-dominated sorting genetic algorithm (NSGA-II) approach is used to find a set of Pareto-optimal solutions. The torsional effects due to irregularities of the building and/or unsymmetrical placements of the dampers are taken into account through the 3-D modeling of the building. Finally, the comparison of the results shows that the probabilistic robust STMD system is capable of providing a reduction of about 52%, 42.5%, and 37.24% on the maximum displacement, velocity, and acceleration of the building top story, respectively.

• Journal of Biosystems Engineering
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• v.17 no.4
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• pp.354-362
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• 1992

This study was intended to examine feasibility of sizing and color grading of Fuji apple with black/white image processing system, to develop a device with which the whole surface of an apple could be captured by one camera, and to develop an algorithm for a high speed sorting. The results are summarized as follows : 1. The black/white image processing system used in this study showed a maximum error of 1.3% in area measurement with a reference figure while the focusing point of camera and location of the reference figure were changed within a certain range. 2. As the result of evaluating four automatic image segmentation algorithms with apple images, Histogram Clustering Method was the best in terms of computation time and accuracy. 3. The fast algorithm for analyzing size and coloration of apple was developed. 4. The whole surface of an apple could be captured in an image frame with two mirrors installed on the both sides of the sample. The total area of the image representing the whole surface showed a correlation of 0.995 with the weight of apple. 5. The gray level when a particular band pass filter was mounted on the camera showed high correlation with 'L' and 'a' values of Hunt color scale and could represent the coloration of apple.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.395-402
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• 2002

In the conventional public switched telephone network(PSTN), there are various types of modulation that can be used in ADSL to offer fast data communication, two of which are CAP(Carrierless Amplitude Phase) and DMT(Discrete MultiTone). As we consider the current situation, DMT is getting more predominant in the market than CAP. One of the reasons is that it gives high performance in spite of its high complexity Since DMT divides the full range of bandwidth into 256 sub-channels, it can be highly adaptive in the circumstances, where the problems of attenuation and noise caused by the propagation distance are very crucial. In this paper, a new bit loading algorithm for DMT modulation is proposed. The proposed algorithm can be efficiently implemented in a way that it requires less computation than the conventional modulation techniques. In contrast to the conventional algorithms which perform sorting processing, the proposed algorithm uses look-up tables to reduce the repetition of calculation. Consequently, it is shown that less processing time and lower complexity can be achieved.

• Journal of Korea Multimedia Society
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• v.3 no.6
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• pp.674-684
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• 2000

One key obstacle which has been identified in achieving parallel processing is to communicate effectively between processors during execution. One approach to achieving an optimal delay time is to use expander graph. The networks and algorithms which are based on expander graphs are successfully exploited to yield fast parallel algorithms and efficient design. The AKS sorting algorithm in time O(logN) which is an important result is based on the use of expanders. The expander graph also can be applied to construct a concentrator and a superconcentrator. Since Margulis found a way to construct an explicit linear expander graph, several expander graphs have been developed. But the proof of existence of such graphs is in fact provided by a nonconstructive argument. We investigate the expander network on the hypercube network. We prove the expansion of a sin81e stage hypercube network and extend this from a single stage to multistage networks. The results in this paper provide a theoretical analysis of expansion in the hypercube network.