• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.15 no.1 s.94
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• pp.12-19
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• 2005

This paper proposed a dual actuator using Bimorph PZT for information storage device based on prove array NSOM(near-field scanning optical microscopy). The gap between the media and the optical head should be maintained within the optical tolerance. Therefore, a new actuator having high sensitivity is required. Bimorph PZT, which has fast access time and high sensitivity characteristic, is suitable for this precise actuating system. This paper is focused on derivation of mathematical model of dual Bimorph PZT actuator and control algorithm. Hamilton's principle was used for mathematical model. The model is verified by FEA(finite element analysis), and compared with experimental results. Different control algorithms were used for two Bimorph PZT actuating same direction and opposite direction. The gap between recording media and optical head was controlled within 20nm in experiment.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.5
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• pp.1061-1066
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• 2012

A digital memory has been widely used as a device for storing information due to its reliable, fast and relatively simple control circuit. However, the storage of the digital memory will be limited by the inablility to make smaller linewidths. One way to dramatically increase the storeage capability of the memory is to change the type of stored data from digital to analog. The analog memory fabricated in a standard single poly 0.6um CMOS process has been developed. Single cell and adjacent circuit block for programming have been designed and characterized. Applications include low-density non-volatile memory, control of redundancy in SRAM and DRAM memories, ID or security code registers, and image and sound memory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.5
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• pp.529-538
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• 1992

Recently, image signal processing techniques for HDTV signal have been drastically developed. This kind of skill improvement on signal processing need specific memory device for video signal. in this paper, data latch scheme which implements CMOS flip-flop to hold Information from in-put strobe and new reading method is devised to attain a proper access time suitable for HDTY signal. Compared with conventional write scheme, data latch method has two procedures to complete write operation : bit line write and storage cell write, enabling concurrent I /0 operation at the same address. Also, fast read access is possible through the method similar to static column mode and the separated read word line.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.235-243
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• 2018

NAND flash memory has been widely used for embedded systems as storage device and the flash memory file systems such as JFFS2, YAFFS/YAFFS2 have been adopted by these embedded systems. The flash memory file systems provide the high performance and overcome the limitations of flash memory. However, these file systems don't solve the slow mount time problem when a sudden power failure happens. In this paper, we proposed a flash memory management method for enhancing the recovery performance. The proposed method manages the flash memory block type and stores the block type information at recovery image block. When file operations are occurred, our method stores the file information at the metadata block before and after the file operation. When mounting the flash memory, our method only scans the recovery image blocks and metadata blocks. The proposed method reduces the mount time by seeking the metadata block locations fast by using the recovery image blocks. We implemented the proposed method and evaluation results show that our method reduces the mount time 13 ~ 46 % compared with YAFFS2.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.2251-2252
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• 2008

Recently, voltage sag from sudden increasing loads is also one of the major problems inside the utility network. In order to compensate the voltage sag problem, power compensation device systems could be a good solution method. In case of voltage sag, an energy source is needed to overcome the energy loss caused by the voltage sag. Superconducting Magnetic Energy Storage (SMES) is a very promising source of this energy due to its fast response of charging and discharging time. Before constructing the power electronic delivering system for the SMES, it is necessary to simulate the system to understand its behavior. Nowadays, a lot of devices have been developed to compensate voltage sag such as Dynamic Voltage Restorer (DVR), Distribution Static Compensator (D-STATCOM) and Uninterruptible Power Supply (UPS). In this paper, focus is given only on DVR system which will be simulated by using PSCAD/EMTDC software.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2002.05a
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• pp.373-377
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• 2002

In this study, we suggested a slim-type actuator that can be controlled in radial direction for compensating coma aberration in high-capacity optical storage devices. To deal successfully with narrow space in slim-type optical pick-up for notebook pc device, additional yokes for tilting motion are integrated into main yoke of the actuator. And the location of tilting coils is determined for mass-b3lancing effect to achieve optimal configuration for high driving sensitivity. We also suggested new concept of lens holder to guarantee excellent stability of control system by enhancing the gain margin at secondary resonant frequency. The concept was realized by forming damping sections in the lens holder, which prevent vibrational energy from transferring to lens. An exclusive measurement system was newly developed for fast and precise measurement of dynamic characteristics of actuators and utilized for the practical use. We hope to make good use of this system also in time to come.

• Journal of the Korea Society of Computer and Information
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• v.20 no.11
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• pp.1-8
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• 2015

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.108-109
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• 2012

This talk will begin with the demonstration of facile synthesis of silicon nanostructures using the magnesiothermic reduction on silica nanostructures prepared via self-assembly, which will be followed by the characterization results of their performance for energy storage. This talk will also report the fabrication and characterization of highly porous, stretchable, and conductive polymer nanocomposites embedded with carbon nanotubes (CNTs) for application in flexible lithium-ion batteries. It will be presented that the porous CNT-embedded PDMS nanocomposites are capable of good electrochemical performance with mechanical flexibility, suggesting these nanocomposites could be outstanding anode candidates for use in flexible lithium-ion batteries. Directed self-assembly (DSA) of block copolymers (BCPs) can generate uniform and periodic patterns within guiding templates, and has been one of the promising nanofabrication methodologies for resolving the resolution limit of optical lithography. BCP self-assembly processing is scalable and of low cost, and is well-suited for integration with existing semiconductor manufacturing techniques. This talk will introduce recent research results (of my research group) on the self-assembly of Si-containing block copolymers for the achievement of sub-10 nm resolution, fast pattern generation, transfer-printing capability onto nonplanar substrates, and device applications for nonvolatile memories. An extraordinarily facile nanofabrication approach that enables sub-10 nm resolutions through the synergic combination of nanotransfer printing (nTP) and DSA of block copolymers is also introduced. This simple printing method can be applied on oxides, metals, polymers, and non-planar substrates without pretreatments. This talk will also report the direct formation of ordered memristor nanostructures on metal and graphene electrodes by the self-assembly of Si-containing BCPs. This approach offers a practical pathway to fabricate high-density resistive memory devices without using high-cost lithography and pattern-transfer processes. Finally, this talk will present a novel approach that can relieve the power consumption issue of phase-change memories by incorporating a thin $SiO_x$ layer formed by BCP self-assembly, which locally blocks the contact between a heater electrode and a phase-change material and reduces the phase-change volume. The writing current decreases by 5 times (corresponding to a power reduction of 1/20) as the occupying area fraction of $SiO_x$ nanostructures varies.

• Journal of Energy Engineering
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• v.29 no.1
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• pp.44-51
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• 2020

The importance of ESS has been emphasized due to stabilization of power demand due to deterioration of network reliability and expansion of renewable energy sources. ESS (Energy Storage System) stores the remaining power and uses it when necessary to meet the power demand, and build the ESS system mainly in conjunction with solar and wind power. In this paper, we propose a home PV Charging Module using the Master-Slave method which is effective for low insolation. After designing the module, Fast MPPT algorithm is applied to generate the maximum output from the nonlinear output characteristics of the PV modules. The average power value for the input of PV Charging Module was 296.90 W and the output power was 289.60 W, which averaged 97.54%.

• Journal of the Korea Society of Computer and Information
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• v.26 no.11
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• pp.11-19
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• 2021

In this paper, we propose a prototype platform combined with the power management system using, as an auxiliary power storage device, a supercapacitor that can be fast charged and discharged with high power efficiency as well as semi-permanent charge and discharge cycle life. For the proposed platform, we designed a technique which is capable of detecting the state of power cutoff or resumption of power supplied from the solar panel in accordance with physical environment changes through an interrupt attached to the micro-controller was developed. To prevent data loss in a computing environment in which continuous power supply is not guaranteed, we implemented a low-level system software in the micro-controller to transfer program context and data in volatile memory to nonvolatile memory when power supply is cut off. Experimental results shows that supercapacitors effectively supply temporary power as auxiliary power storage devices. Various benchmarks also confirm that power state detection and transfer of program context and data from volatile memory to nonvolatile memory have low overhead.