• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.10a
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• pp.223-225
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• 2021

Modular multiplication is a key operation for point scalar multiplication of ECC, and is the most important factor affecting the performance of ECC processor. This paper describes a design of a 256-bit modular multiplier that adopts 3-way Toom-Cook multiplication algorithm and modified fast reduction algorithm. One 90-bit multiplier and three 264-bit adders were used to optimize the hardware size and the number of clock cycles required. The modular multiplier was verified by implementing it using Zynq UltraScale+ MPSoC device and the modular multiplication operation takes 15 clock cycles.

• Journal of KIISE:Information Networking
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• v.31 no.6
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• pp.566-572
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• 2004

In this paper, we define the secure authentication model to provide a mobile node with global roaming service and integrate the Fast Handoff scheme with our approach to minimize the service latency. By starting the AAA(Authentication, Authorization and Account) procedure with Fast Handoff simultaneously when a roaming occurs, authentication latency is reduced significantly and provision of fast and seamless service is possible. The previous works such as IPsec(Internet Protocol Security), RR (Return Routability) and AAA define the procedures performed after the completion of Layer2 Handoff which leads us to study a way of providing the real time and QoS guaranteed service during this period. The proposed scheme is for this goal and when appling it to roaming environment it shows the cost reduction up to 55% and 17% for the case of the MN receiving the FBACK and not respectively before L2 Handoff occurs.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.121-130
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• 2017

NAND flash memory has advantages of non-volatility, little power consumption and fast access time. However, it suffers from inability that does not provide to update-in-place and the erase cycle is limited. Moreover, the unit of read/write operation is a page and the unit of erase operation is a block. Therefore, erase operation is slower than other operations. The AGC, the proposed garbage collection policy focuses on not only garbage collection time reduction for real-time guarantee but also wear-leveling for a flash memory lifetime. In order to achieve above goals, we define three garbage collection operating modes: Fast Mode, Smart Mode, and Wear-leveling Mode. The proposed policy decides the garbage collection mode depending on system CPU usage rate. Fast Mode selects the dirtiest block as victim block to minimize the erase operation time. However, Smart Mode selects the victim block by reflecting the invalid page number and block erase count to minimizing the erase operation time and deviation of block erase count. Wear-leveling Mode operates similar to Smart Mode and it makes groups and relocates the pages which has the similar update time. We implemented the proposed policy and measured the performance compare with the existing policies. Simulation results show that the proposed policy performs better than Cost-benefit policy with the 55% reduction in the operation time. Also, it performs better than Greedy policy with the 87% reduction in the deviation of erase count. Most of all, the proposed policy works adaptively according to the CPU usage rate, and guarantees the real-time performance of the system.

• Journal of Theoretical and Applied Mechanics
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• v.3 no.1
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• pp.1-15
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• 2002

Reduction methods for large structural systems have been reviewed. Mai emphasis is put on the dynamic reduction. Recently, the computing resources and technologies have been expanded so fast that the huge matrices Invoked In the analysis of structural system can be processed without serious difficulties. For most users, however, the computer facilities are limited and the system reductions in some forms are required. The reduction procedure in static problems is simple and straightforward. The major task is the book-keeping in computations. In dynamic problems and structural optimization. however. the problem is much more complicated. The problem is, in general, nonlinear and hence the exact solution is not available. Therefore, approximate solutions are sought in an iterative manner. A proper convergence criterion needs to be employed in order to get an accurate solution efficiently. Several research works have been reported fer the structural optimization combined with system reductions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.6C
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• pp.565-571
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• 2007

In order to improve PAPR (Peak-to-Average Power Ratio) reduction performance of the conventional SLM (Selective Mapping) for OFDM (Orthogonal Frequency Division Multiplexing) signals, we propose an effective SLM-PRSC (PAPR Reduction Sub-Carrier) hybrid scheme. In the proposed scheme, after performing the SLM for the frequency domain OFDM symbol excluding pre-determined PRSC positions, the SLM-PRSC hybrid sequence with the lowest PAPR generated by adding the time domain PRSC sequence to the results of the SLM, is selected as the transmitted OFDM signal. Since the identical PRSC sequences generated a priori are repeatedly used for every OFDM symbol, excessive IFFT (inverse Fast Fourier Transform) calculation is avoided. Simulation results show that the proposed scheme significantly improves the PAPR reduction performance of the conventional SLM, while avoiding excessive increase of IFFT calculation and the overhead for the SLM.

• Journal of KIISE:Information Networking
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• v.35 no.4
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• pp.301-310
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• 2008

In the existing literature, the handover process reveals numerous problems manifested by high movement detection latency. FMIPv6 can reduce packet loss using a tunnel-based handover mechanism. However, this mechanism may cause performance degradation due to the out-of-sequence packets. Recently. Proxy Mobile IPv6 is proposed for network-based mobility management to reduce overhead in mobile node. PMIPv6 can decrease handover latency which related overhead in MN by using network agent. In this paper, we proposed optimized fast handover scheme called Fast Proxy Mobile IPv6 (EF-PMIPv6). The proposed EF-PMIPv6 can support fast handover using fast IAPP and ND schemes. Further, a mathematical analysis is provided to show the benefits of our scheme. In the analysis, various parameters are used to compare our scheme with the current procedures, while our approach focuses on the reduction of handover latency.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.3
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• pp.1195-1211
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• 2016

The emerging video coding standard High Efficiency Video Coding (HEVC) has shown almost 40% bit-rate reduction over the state-of-the-art Advanced Video Coding (AVC) standard but at about 40% computational complexity overhead. The main reason for HEVC computational complexity is the inter prediction that accounts for 60%-70% of the whole encoding time. In this paper, we propose several fast coding unit (CU) encoding schemes based on the Merge mode and motion estimation information to reduce the computational complexity caused by the HEVC inter prediction. Firstly, an early Merge mode decision method based on motion estimation (EMD) is proposed for each CU size. Then, a Merge mode based early termination method (MET) is developed to determine the CU size at an early stage. To provide a better balance between computational complexity and coding efficiency, several fast CU encoding schemes are surveyed according to the rate-distortion-complexity characteristics of EMD and MET methods as a function of CU sizes. These fast CU encoding schemes can be seamlessly incorporated in the existing control structures of the HEVC encoder without limiting its potential parallelization and hardware acceleration. Experimental results demonstrate that the proposed schemes achieve 19%-46% computational complexity reduction over the HEVC test model reference software, HM 16.4, at a cost of 0.2%-2.4% bit-rate increases under the random access coding configuration. The respective values under the low-delay B coding configuration are 17%-43% and 0.1%-1.2%.

• Journal of Broadcast Engineering
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• v.2 no.1
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• pp.45-55
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• 1997

In this paper, we propose a fast algorithm with adaptive thresholding for the wavelet transform (WT) based blocking artifact reduction. In the fast algorithm, all processings that are equivalent to the processing in WT domain of the first and second scale are performed in spatial domain. In the adaptive thresholding, the threshold values used to classify the block boundary are selected adaptively according to each input image by using the statistical properties of the WT of the coded signal at block boundary and at block center, which can be obtained in spatial domain. Experimental results showed that the proposed fast algorithm is about 10 times faster than the WT-based algorithm. It also was found that the postprocessing with proposed adaptive thresholding yields some PSNR improvement and better subjective quality over that with nonadaptive thresholding which has best performance at high compression ratios of a certain .image, even at low compression ratios.

• ETRI Journal
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• v.31 no.6
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• pp.784-794
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• 2009

We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10A
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• pp.1548-1553
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• 2000

In this paper, an effective peak power reduction scheme for a downlink OFDM-CDMA system is proposed. Using the partial parallel transform(PPT) structure, peak-to-average power ratio(PAPR) can be reduced. The patterns of inputs of Inverse Fast Fourier Transform(IFFT) are more randomized in this structure by allotting the subcarriers to each users. At the cost of complexity we can obtain reduced PAPR and multiple access interference(MA) Computer simulations are carried out from the viewpoint of PAPR and demonstrated the improved PAPR performance.