• 제목/요약/키워드: Fabrication process variation

검색결과 138건 처리시간 0.032초

다중조사 복셀 매트릭스 스캐닝법을 이용한 이광자 중합에 의한 마이크로 3차원 곡면형상 제작 (Fabrication of Three-Dimensional Curved Microstructures by Two-Photon Polymerization Employing Multi-Exposure Voxel Matrix Scanning Method)

  • 임태우;박상후;양동열;공홍진;이광섭
    • 폴리머
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    • 제29권4호
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    • pp.418-421
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    • 2005
  • 본 연구에서는 나노/마이크로 소자 및 MEMS 제작에 활용가능하고 또한 수십 마이크로미터 크기의 3차원 곡면을 가진 형상을 제작하기 유리한 이광자 광중합을 이용한 다중조사 복셀 매트릭스 스캐닝법(multi-exposure voxel matrix scanning method)에 의한 나노 복화공정을 개발하였다. 이 공정을 통하여는 높이에 따라 14가지의 색을 가진 등고선으로 표현된 3차원 자유곡면 형상을 적층방식이 아닌 단일 층으로 3차원으로 제작할 수 있다. 여기서 수광각도가 1.25인 집광렌즈를 사용하여 레이저의 조사시간에 따라 1.2 um에서 6.4 um까지 변하는 복셀의 높이 차이를 이용하여 3차원 곡면 제작이 가능하다. 본 연구의 유용성을 검토하기 위하여 몇 가지 3차원 곡면형상을 초미세 입체 패터닝 공정에서 사용하는 일반적인 적층방식을 사용하지 않고 단층으로 제작하여 시간을 단축하였다.

실리콘 웨이퍼 연마에서의 Break-in 모니터링 (Monitoring of Break-in time in Si wafer polishing)

  • 정석훈;박범영;박성민;이상직;이현섭;정해도;배소익;최은석;백경록
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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    • pp.360-361
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    • 2005
  • Rapid progress in IC fabrication technology has strong demand in polishing of silicon wafer to meet the tight specification of nanotopography and surface roughness. One of the important issues in Si CMP is the stabilization of polishing pad. If a polishing pad is not stabilized before main Si wafer polishing process, good polishing result can not be expected. Therefore, new pad must be subjected into break-in process using dummy wafers for a certain period of time to enhance its performance. After the break-in process, the main Si wafer polishing process must be performed. In this study, the characteristics of break-in process were investigated in Si wafer polishing. Viscoelastic behavior, temperature variation of pad and friction were measured to evaluate the break-in phenomenon. Also, it is found that the characteristic of the break-in seems to be related to viscoelastic behavior of pad.

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Virtual Metrology for predicting $SiO_2$ Etch Rate Using Optical Emission Spectroscopy Data

  • Kim, Boom-Soo;Kang, Tae-Yoon;Chun, Sang-Hyun;Son, Seung-Nam;Hong, Sang-Jeen
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2009년도 제38회 동계학술대회 초록집
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    • pp.464-464
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    • 2010
  • A few years ago, for maintaining high stability and production yield of production equipment in a semiconductor fab, on-line monitoring of wafers is required, so that semiconductor manufacturers are investigating a software based process controlling scheme known as virtual metrology (VM). As semiconductor technology develops, the cost of fabrication tool/facility has reached its budget limit, and reducing metrology cost can obviously help to keep semiconductor manufacturing cost. By virtue of prediction, VM enables wafer-level control (or even down to site level), reduces within-lot variability, and increases process capability, $C_{pk}$. In this research, we have practiced VM on $SiO_2$ etch rate with optical emission spectroscopy(OES) data acquired in-situ while the process parameters are simultaneously correlated. To build process model of $SiO_2$ via, we first performed a series of etch runs according to the statistically designed experiment, called design of experiments (DOE). OES data are automatically logged with etch rate, and some OES spectra that correlated with $SiO_2$ etch rate is selected. Once the feature of OES data is selected, the preprocessed OES spectra is then used for in-situ sensor based VM modeling. ICP-RIE using 葰.56MHz, manufactured by Plasmart, Ltd. is employed in this experiment, and single fiber-optic attached for in-situ OES data acquisition. Before applying statistical feature selection, empirical feature selection of OES data is initially performed in order not to fall in a statistical misleading, which causes from random noise or large variation of insignificantly correlated responses with process itself. The accuracy of the proposed VM is still need to be developed in order to successfully replace the existing metrology, but it is no doubt that VM can support engineering decision of "go or not go" in the consecutive processing step.

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Photo Resistor Reflow 방법을 이용한 오프셋 마스크를 이용하지 않는 새로운 자기 정합 폴리 실리콘 박막 트랜지스터 (Self-aligned Offset Gated Poly-Si TFTs by Employing a Photo Resistor Reflow Process)

  • 박철민;민병혁;한민구
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1995년도 하계학술대회 논문집 C
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    • pp.1085-1087
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    • 1995
  • A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

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변위센서응용을 위한 피라미드형 실리콘 턴널링소자의 제조 (Fabrication of the pyramid-type silicon tunneling devices for displacement sensor applications)

  • 마대영;박기철;김정규
    • 센서학회지
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    • 제9권3호
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    • pp.177-181
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    • 2000
  • 턴널링 전류는 전극사이의 거리에 지수적으로 비례한다. 따라서 턴널링 전류의 변화측정을 통하여 전극간격의 미세변위를 측정할 수 있다. 본 실험에서는 micro-tip과 membrane사이에 턴널링 전류가 흐르는 피라미드형 실리콘 턴널링소자를 micro-electro-mechanical systems (MEMS) 공정을 이용하여 제조하였다. 단결정 실리콘을 KOH 용액안에서 이방성 에칭 시켜 micro-tip을 제조하였으며, 이때 $SiO_2$막을 마스크로 사용하였다 $Si_3N_4$막으로 membrane을 형성하였다. 마스크 방향에 따른 에칭 진행과정의 차이를 조사하였으며 membrane으로 사용한 $Si_3N_4$막의 stiffness를 측정하였다. 실험으로 측정하기 어려운 영역의 $Si_3N_4$막 stiffness 예측을 위한 모델식을 제시하였다.

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Quatrz 웨이퍼의 직접접합과 극초단 레이저 가공을 이용한 체내 이식형 혈압센서 개발 (Development of Implantable Blood Pressure Sensor Using Quartz Wafer Direct Bonding and Ultrafast Laser Cutting)

  • 김성일;김응보;소상균;최지연;정연호
    • 대한의용생체공학회:의공학회지
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    • 제37권5호
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    • pp.168-177
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    • 2016
  • In this paper we present an implantable pressure sensor to measure real-time blood pressure by monitoring mechanical movement of artery. Sensor is composed of inductors (L) and capacitors (C) which are formed by microfabrication and direct bonding on two biocompatible substrates (quartz). When electrical potential is applied to the sensor, the inductors and capacitors generates a LC resonance circuit and produce characteristic resonant frequencies. Real-time variation of the resonant frequency is monitored by an external measurement system using inductive coupling. Structural and electrical simulation was performed by Computer Aided Engineering (CAE) programs, ANSYS and HFSS, to optimize geometry of sensor. Ultrafast laser (femto-second) cutting and MEMS process were executed as sensor fabrication methods with consideration of brittleness of the substrate and small radial artery size. After whole fabrication processes, we got sensors of $3mm{\times}15mm{\times}0.5mm$. Resonant frequency of the sensor was around 90 MHz at atmosphere (760 mmHg), and the sensor has good linearity without any hysteresis. Longterm (5 years) stability of the sensor was verified by thermal acceleration testing with Arrhenius model. Moreover, in-vitro cytotoxicity test was done to show biocompatiblity of the sensor and validation of real-time blood pressure measurement was verified with animal test by implant of the sensor. By integration with development of external interrogation system, the proposed sensor system will be a promising method to measure real-time blood pressure.

효소연료전지의 Anode 제조조건이 성능에 미치는 영향 (Effect of Fabrication Method of Anode on Performance in Enzyme Fuel Cells)

  • 이세훈;황병찬;이혜리;김영숙;추천호;나일채;박권필
    • Korean Chemical Engineering Research
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    • 제53권6호
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    • pp.667-671
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    • 2015
  • Anode는 효소를 이용한 효소전극과 cathode는 PEMFC용 전극을 이용해 효소연료전지를 구동하였다. 효소 anode는 graphite 분말과 효소로서 글루코스 산화제, 전자매개체로 ferrocene을 혼합해 압축해서 만들고 Nafion 이오노머로 코팅하였다. Anode 제조조건을 변화시키며 성능을 측정해 효소 anode 제조 최적조건을 찾았다. 효소 anode 압축 시 최적 압력은 8.89 MPa이고, 효소 anode의 graphite 성분비가 60%일 때 최고의 출력밀도를 나타냈다. Anode 기질 용액의 최적 glucose 농도는 1.7mol/l이었다. 효소 anode는 Nafion 용액에 1초, 2회 침지에 의해 안정화되었다.

MOD법에 의한 강유전성 $Sr_xBi_yTa_2O_{9+\alpha}$(SBT) 박막의 제조 및 후열처리 효과에 관한 연구 (Fabrication and Post-Annealing Effects of Ferroelectric $Sr_xBi_yTa_2O_{9+\alpha}$(SBT) Thin Films by MOD Process)

  • 정병직;신동석;윤희성;김병호
    • 한국전기전자재료학회논문지
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    • 제11권3호
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    • pp.229-236
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    • 1998
  • Ferroelectric $Sr_xBi_yTa_2O_{9+\alpha}$/(0.7$\leqSr\leq1.0,\; 2.0\leqBi\leq2.6)$ solutions were prepared by MOD (Metalorganic Deposition) process. These solutions were made into thin films with thickness ranging from 1500~2000${\AA}$ by spin coating. The phase transformation of the SBT thin films by variation of annealing temperature and annealing time were observed using high temperature XRD and SEM. The crystallization and grain growth of SBT thin film were accomplished at $800^{\circ}C$ for 30 minutes after deposition of Pt top electrode by sputtering to prevent electrical breakdown. Ferroelectric properties of the SBT thin films were measured in the range of $\pm$3V\; and\; \pm5V$. The specimen with composition ratio of Sr/Bi/Ta (0.8/2.4/2.0) has the excellent ferroelectric properties ; $2P_r = 10.5,\; 13.2\muC/cm^2 \;at\; \pm3V\; and\; \pm5V$ respectively. Observing the post annealed Pt/SBT/Pt interface by SEM, it was found that Pt electrode sputtered on to the SBT thin film penetrated into the hollow on the SBT thin film, thus decreasing the effective insulation thickness. The effective insulation thickness recovered by post annealing, and this was confirmed by leakage current density measurement.

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SERRATION MECHANISM OF AA5182/POLYPROPYLENE/AA5182 SANDWICH SHEETS

  • Kim, K.J.
    • International Journal of Automotive Technology
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    • 제7권4호
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    • pp.485-492
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    • 2006
  • The AA5182/polypropylene/AA5182(AA/PP/AA) sandwich sheets have been developed for application to automotive body panels in future lightweight vehicles with significant weight reduction. It has been reported that the AA5182 aluminum sheet shows $L\"{u}ders$ band because of dissolved Mg atoms that cause fabrication process problem, especially surface roughness. The examination of serration behavior has been made after the tensile deformation of the AA/PP/AA sandwich sheets as well as that of the AA5182 aluminum skins at room and elevated temperatures. All sandwich sheets and the AA5182 aluminum skin showed serration behavior on their flow curves. However, the magnitude of serration was significantly diminished in the sandwich sheet with high volume fraction of the polypropylene core. According to the results of the analysis of the surface roughness following the tensile test, $L\"{u}ders$ band depth of the sandwich sheet evidently showed lower than that of the AA5182 aluminum skin. The strain rate sensitivity, m-value, of the AA5182 aluminum skin was -0.006. By attaching these skins to the polypropylene core, which has relatively large positive value of 0.050, m-value of the sandwich sheets changed to the positive value. The serration mechanism of the sandwich sheets was quantitatively investigated in the point of the effect on polypropylene thickness variation, that on the strain rate sensitivity and that on the localized stress state.

박막 알루미늄을 이용한 규칙적으로 정렬된 나노급 미세기공 어레이 제조기술 개발 (Development of Fabrication Technique of Highly Ordered Nano-sized Pore Arrays using Thin Film Aluminum)

  • 이재홍;김창교
    • 한국전기전자재료학회논문지
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    • 제18권8호
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    • pp.708-713
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    • 2005
  • An alumina membrane with nano-sized pore array by anodic oxidation using the thin film aluminum deposited on silicon wafer was fabricated. It Is important that the sample prepared by metal deposition method has a flat aluminum surface and a good adhesion between the silicon wafer and the thin film aluminum. The oxidation time was controlled by observation of current variation. While the oxalic acid with 0.2 M was used for low voltage anodization under 100 V, the chromic acid with 0.1 M was used for high voltage anodization over 100 V. The nano-sized pores with diameter of $60\~120$ nm was obtained by low voltage anodization of $40\~80$ V and those of $200\~300$ nm was obtained by high voltage anodization of $140\~200$ V. The pore widening process was employed for obtaining the one-channel with flat surface because the pores of the alumina membrane prepared by the fixed voltage method shows the structure of two-channel with rough surface. Finally, the sample was immersed to the phosphoric acid with 0.1 M concentration to etching the barrier layer.