• Title/Summary/Keyword: Fabrication cost

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Divided Generation Algorithm of Universal Test Set for Digital CMOS VLSI (디지털 CMOS VLSI의 범용 Test Set 분할 생성 알고리듬)

  • Dong Wook Kim
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.11
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    • pp.140-148
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    • 1993
  • High Integration ratio of CMOS circuits incredily increases the test cost during the design and fabrication processes because of the FET fault(Stuck-on faults and Stuck-off faults) which are due to the operational characteristics of CMOS circuits. This paper proposes a test generation algorithm for an arbitrarily large CMOS circuit, which can unify the test steps during the design and fabrication procedure and be applied to both static and dynaic circuits. This algorithm uses the logic equations set for the subroutines resulted from arbitrarily dividing the full circuit hierarchically or horizontally. Also it involves a driving procedure from output stage to input stage, in which to drive a test set corresponding to a subcircuit, only the subcircuits connected to that to be driven are used as the driving resource. With this algorithm the test cost for the large circuit such as VLSI can be reduced very much.

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Optimum design of stiffened plates for static or dynamic loadings using different ribs

  • Virag, Zoltan;Jarmai, Karoly
    • Structural Engineering and Mechanics
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    • v.74 no.2
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    • pp.255-266
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    • 2020
  • The main requirements of modern welded metal structures are the load-carrying capacity (safety), fitness for production, and economy. The primary objective of attaching longitudinal stiffeners is to improve the buckling strength of relatively thin compression panels. This paper gives several comparisons for stiffened plates with different loadings (static, dynamic), different shape of stiffeners (flat, L-shape, trapezoidal), different steel grades, and different welding technologies (SMAW, GMAW, SAW), different costs to show the necessity of a combination of design, fabrication and economic aspects. Safety and fitness for production are guaranteed by fulfilling the design and fabrication constraints. The economy is achieved by minimizing the cost function. It is shown that the optimum sizes depend on the welding technology, the material yield stress, the profile of the stiffeners, the load cycles and the place of the production.

A FEASIBILITY STUDY ON THE NUMERICAL PRE-ASSEMBLY SIMULATION USING 3D LASER SCANNING MEASUREMENT

  • Kyoungmin Kim ;Seok Kim ;Chan-Hyuk Park ;Kyong Ju Kim
    • International conference on construction engineering and project management
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    • 2005.10a
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    • pp.1193-1198
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    • 2005
  • The pre-assembly takes a large portion of the fabrication cost of steel bridges. In order to save the fabrication cost through the improvement of the conventional pre-assembling process, this research investigates a numerical pre-assembly simulation as an alternative to current pre-assembling process. The 3D laser scanning was utilized in site and measuring data for steel box were analyzed. The productivity of pre-assembly simulation system is compared with the conventional pre-assembling system. This paper identifies feasibility on the alternative pre-assembling process and then proposes the scheme of the pre-assembly simulation system development satisfying the current pre-assembly inspection of standards.

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Fabrication and Analysis of Chirped Fiber Bragg Gratings by Thermal Diffusion

  • Cho, Seung-Hyun;Park, Jae-Dong;Kim, Byoung-Whi;Kang, Min-Ho
    • ETRI Journal
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    • v.26 no.4
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    • pp.371-374
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    • 2004
  • We propose and demonstrate a fabrication method of chirped fiber gratings by a thermal diffusion process. The method could suggest a direction for a simple and cost-effective implementation of chirped fiber grating-based devices.

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Transparent Conductor-embedding Si for High-performing Hetrojunction Photoelectric Devices

  • Kim, Joondong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.444.2-444.2
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    • 2014
  • Transparent conductors (TCs) are typically applied as an ohmic contact layer for photoelectric devices. Recent researches have illuminated a unique rectifying-junction design between a transparent conductor and a semiconductor layer. This approach may lead a significant reduction of device-fabrication steps and cost. A high-performing heterojunction device is presented, which provided significant photoelectric responses. This covers the fabrication processes, rectifying-junction formations and device analyses.

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Fabrication of Nanocomposite Powders by Sonochemical Method

  • Hayashi, Yamato;Sekino, Tohru;Niihara, Koichi
    • Journal of Powder Materials
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    • v.8 no.3
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    • pp.207-209
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    • 2001
  • Nano particles have recently been a major research interest, motivated by their unusual physical and chemical properties. Such particles can be synthesized using physical and chemical methods. The physical methods need expensive installation like vacuum induction furnace, whereas in chemical methods the process in generally very simple and low cost. In this study, simple and new fabrication process by using ultrasound was investigated to prepare the nano-sized metal particles on various powders at room temperature.

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Development of 121 pins/mm2 High Density Probe Card using Micro-spring Architecture (마이크로 스프링 구조를 갖는 121 pins/mm2 고밀도 프로브 카드 제작기술)

  • Min, Chul-Hong;Kim, Tae-Seon
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.20 no.9
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    • pp.749-755
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    • 2007
  • Recently, novel MEMS probe cards can support reliable wafer level chip test with high density probing capacity. However, manufacturing cost and process complexity are crucial weak points for low cost mass production. To overcome these limitations, we have developed micro spring structured MEMS probe card. For fabrication of micro spring module, a wire bonder and electrolytic polished gold wires are used. In this case, stringent tension force control is essential to guarantee the low level contact resistance of micro spring for reliable probing performance. For this, relation between tension force of fabricated probe card and contact resistance is characterized. Compare to conventional probe cards, developed MEMS probe card requires fewer fabrication steps and it can be manufactured with lower cost than other MEMS probe cards. Also, due to the small contact scratch patterns, we expect that it can be applied to bumping types chip test which require higher probing density.