• Journal of Korean Institute of Industrial Engineers
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• v.23 no.1
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• pp.129-146
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• 1997

In traditional approaches to scheduling problems, a single dispatching rule was used by all machines in a system. However, since the situation of each machine generally differs from those of other machines, it is reasonable to apply a different dispatching rule to each machine responding to its given situation. In this regard, we introduce the concept of spatial adaptation and examine its effectiveness by simulation. In the spatial adaptation, each machine in a system selects an appropriate dispatching rule in order to improve productivity while it strives to be in harmony with other machines. This study proposes an adaptive procedure which produces a reliable dispatching rule for each machine beginning with the bottleneck machine. The dispatching rule is composed of several criteria of which priorities are adaptively weighted. The weights are learned for each machine through systematic simulations. The simulations are conducted according to a Taguchi experimental design in order to find appropriate sets of criteria weights in an efficient and robust way in the context of environmental variations. The proposed method was evaluated in an application to a semiconductor wafer fabrication system. The method achieved reliable performance compared to traditional dispatching rules, and the performance quickly approached the peak after learning for only a few bottleneck machines.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2007.10a
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• pp.162-165
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• 2007

AAO(Anodic Aluminum Oxidation) method has been known that it is practically useful for the fabrication of nano-structures and makes it possible to fabricate the highly ordered nano masters on large surface and even on the 2.5 or 3D surface at low cost comparing to the expensive e-beam lithography or the conventional silicon processing. In this study, by using the multi-step anodizing and etching processes, highly ordered nano patterned master with concave shapes was fabricated. By varying the processing parameters, such as initial matter and chemical conditions; electrical and thermal conditions; time scheduling; and so on, the size and the pitch of the nano pattern can be controlled. Consequently, various alumina/aluminum nano structures can be easily available in any size and shape by optimized anodic oxidation in various aqueous acids. In order to replicate nano patterned master, the resulting good filled uniform nano molded structure through electro-forming process shows the validity of the fabricated nano pattern masters.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2008.05a
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• pp.285-287
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• 2008

AAO(Anodic Aluminum Oxidation) method has been known that it is practically useful for the fabrication of nano-structures and makes it possible to fabricate the highly ordered nano masters on large surface and even on the 2.5 or 3D surface at low cost comparing to the expensive e-beam lithography or the conventional silicon processing. In this study, by using the multi-step anodizing and etching processes, highly ordered nano patterned master with concave shapes was fabricated. By varying the processing parameters, such as initial matter and chemical conditions; electrical and thermal conditions; time scheduling; and so on, the size and the pitch of the nano pattern can be controlled. Consequently, various alumina/aluminum nano structures can be easily available in any size and shape by optimized anodic oxidation in various aqueous acids. In order to replicate nano patterned master, the resulting good filled uniform nano molded structure through electro-forming process shows the validity of the fabricated nano pattern masters.

• IE interfaces
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• v.17 no.spc
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• pp.131-140
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• 2004

The purpose of this paper is to develop and show the efficiency of the URL(Unload Request Logic) and LRL(Load Request Logic) of the dispatcher in the Fab(Fabrication) Manufacturing Execution System. These logics are the core procedures which control the material(wafer and glass substrate) flow efficiently in the semiconductor and LCD fab considering inter-bay as well as intra-bay material flow. We use the present and future status information of the system by look-ahead and the information about the future transportation schedule of Automated Guided Vehicles. The simulation results show that the URL and LRL presented in this paper reduce the average lead time, average and maximum WIP level, and the average available AGV waiting time.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1991.10a
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• pp.77-89
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• 1991

One of the important problems concerning the efficient operation of an automated manufacturing system is the flow control problem. Most research papers about scheduling and control of a FMS consider fabrication, machining and assembly independently. In this paper an effective flow control strategy for a FMS with an assembly subsystem which may be called FMAS (Flexible Machining and Assembly System) is designed using the operation-oriented and, combined Push and Pull control method. The flow control system to be described here could meet production demands with a minimum makespan while satisfying assigned due-dates and keeping a low volume of work-in-process at the same time. The control mechanism also considers machine failures and rush jobs.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.9
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• pp.1330-1335
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• 2012

This paper proposes an automatic measurement sampling method for the semiconductor manufacturing process. The method recommends sampling rates using information of process capability indexes and production scheduling plan within the restricted metrology capacity. In addition, it automatically controls the measurement WIP (Work In Process) using measurement priority values to minimize the measurement risks and optimize the measurement capacity. The proposed sampling method minimizes measurement controls in the semiconductor manufacturing process and improves the fabrication productivity via reducing measurement TAT (Turn Around Time), while guaranteeing the level of process quality.

• Journal of the Society of Naval Architects of Korea
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• v.42 no.2 s.140
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• pp.165-174
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• 2005

Recently, world leading companies on manufacturing field are trying to adopt a PLM methodology, which is a new production paradigm, for a survival and strengthening the competitiveness. Some projects for a digital shipyard including a methodology of a digital simulation framework are going on by Seoul national university and Samsung heavy industry. A Database methodology for a scheduling data, an interfacing methodology for a simulation input and output, and a synchronized simulation related methodology are required for enhancing the value of the digital simulation for shipbuilding. In this paper, such a methodologies and a related case study for a fabrication factory and an assembly factory are presented.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.38 no.4
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• pp.159-167
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• 2015

We consider a wafer lot transfer/release planning problem from semiconductor wafer fabrication facilities to probing facilities with the objective of minimizing the deviation of workload and total tardiness of customers' orders. Due to the complexity of the considered problem, we propose a two-level hierarchical production planning method for the lot transfer problem between two parallel facilities to obtain an executable production plan and schedule. In the higher level, the solution for the reduced mathematical model with Lagrangian relaxation method can be regarded as a coarse good lot transfer/release plan with daily time bucket, and discrete-event simulation is performed to obtain detailed lot processing schedules at the machines with a priority-rule-based scheduling method and the lot transfer/release plan is evaluated in the lower level. To evaluate the performance of the suggested planning method, we provide computational tests on the problems obtained from a set of real data and additional test scenarios in which the several levels of variations are added in the customers' demands. Results of computational tests showed that the proposed lot transfer/planning architecture generates executable plans within acceptable computational time in the real factories and the total tardiness of orders can be reduced more effectively by using more sophisticated lot transfer methods, such as considering the due date and ready times of lots associated the same order with the mathematical formulation. The proposed method may be implemented for the problem of job assignment in back-end process such as the assignment of chips to be tested from assembly facilities to final test facilities. Also, the proposed method can be improved by considering the sequence dependent setup in the probing facilities.