• Publications of The Korean Astronomical Society
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• v.27 no.5
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• pp.419-429
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• 2012

In this paper, we propose a new re-quantization method after FFT processing to prevent the distortion of correlation result of VCS (VLBI Correlation Subsystem). The re-quantization is used to rearrange the data bit so as to reduce the data rate processed as 16-bit of FFT result of VCS. Having done this procedure, we found that the distorted spectrum of correlation result occurred in the delay tracking experiments by the re-quantization method introduced for initial design of VCS. In order to solve this, two kinds of re-quantization method, that is, the comparison and selection-type, are proposed. The first is to re-quantize the FFT result as a valid-bit by comparing with the input data after determining the adequate threshold. The second is manually to select the valid-bit of FFT result after finding the valid-field of data according to the bit-distribution of input data. We confirmed that the second is more effective compared with the first through the experimental result, and it will be implemented without so much modification of applied method in the condition of the limited resource of FPGA. The re-quantization is, however, carried out with 4-bit in the proposed second method for FFT result, and then the distortion of correlation result is also appeared. To fix this problem, the bit for re-quantization is extended to 8-bit. The proposed 8-bit selection-type is effectively verified so that the distortion of correlation result disappeared by applying to VCS in consequence of the simulation and correlation experiments.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.88-95
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• 2002

In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.