• Journal of the Korean Institute of Intelligent Systems
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• v.8 no.5
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• pp.83-97
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• 1998

This paper developes an integrated environment CAD system that can design and implement an accurate and cost-effective FLC automatically. For doing this, an integrated development environment (IDE) (called FADIS; FLC Automatic Design and Implementation Station) is built by the seemless coupling of many existing. CAD tools in an attempt to the FADIS performs various functions such that (1) i~utomatically generate the VHDL components appropriate for the proposed FLC architecture from the various design parameters (2) simulate the generated VHDL code on the Synopsys's VHDL Simulator, (3) automatically compiler, (4) generate the optimized, placed, and routed rawbit files from the synthesized modules by Xilinx's XactStep 6.0, (5) translate the rawbit files into the downloadable ex- [:cution reconfigurable FPGA board (VCC's EVCI), and (7) continuously monitor the control status graphically by communicating the FLC with the controlled target via S-bus. The developed FADIS is tested for its validity by carrying out the overall procedures of designing and implementing the FLC required for the truck-backer upper control, the reduction of control execution time due to the controller's FPGA implementation is verified by comparing with other implementations.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.20 no.1
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• pp.3-16
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• 2010

Recently in the field of the wireless sensor network, many researchers are attracted to pairing cryptography since it has ability to distribute keys without additive communication. In this paper, we propose efficient hardware implementation of ${\eta}_T$ pairing which is one of various pairing scheme. we suggest efficient hardware architecture of ${\eta}_T$ pairing based on parallel processing and register/resource optimization, and then we present the result of our FPGA implementation over GF($2^{239}$). Our implementation gives 15% better result than others in Area Time Product.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.43-51
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• 2008

In this paper, we are implemented low-power structure for Inter prediction, Intra prediction, Deblocking filter, Transform and Quantization blocks in H.264/AVC Encoder. The proposed Inter/Intra prediction blocks are shown 60.2% cell area reduction by adder reduction through Distributed Arithmetic, 44.3% add operation reduction using MUX for hardware share in Deblocking filter block. Furthermore we applied CSD and CSS process to reduce the cell area instead of multipliers that take a lot of area. The FPGA(Field Programmable Gate Array) and ARM Process based H.264/AVC encoder is implemented using proposed low power IPs. The proposed structure Platforms are implemented to interlock with FPGA and ARM processors. H.264/AVC Encoder implementation using Platforms shows that proposed low-power IPs can use H.264/AVC Encoder SoC effectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2109-2116
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• 2014

This paper presents the implementation and design of the advanced WI-FI systems with beam-forming antenna that radiate their power to the direction of user equipment to improve the overall throughput, contrast to the general WI-FI systems equipped with omni-antenna. The system consists of patch array antenna, DSP, FPGA, and Qualcomm's commercial chip. The beam-forming system on the FPGA utilizes the packet information from Qualcomm's commercial chip to control the phase shifters and attenuators of the patch array antenna. The PCI express interface has been used to maximize the communication speed between DSP and FPGA. The directions of arrival of users are managed using the database, and each user is distinguished by the MAC address given from the packet information. When the system wants to transmit a packet to one user, it forms beams to the direction of arrival of the corresponding user stored in the database to maximize the throughput. Directions of arrival of users are estimated using the received preamble in the packet to make its SINR as high as possible. The proposed beam-forming system was implemented using an FPGA and Qualcommm's commercial chip together. The implemented system showed considerable throughput improvement over the existing general AP system with omni-directional antenna in the multi-user communication environment.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.9
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• pp.124-129
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• 2009

Recently, PWM inverter is widely utilized for many industrial applications such as high performance drive and space vector pulse width modulation(SVPWM) inverter which has high voltage ratio and low harmonics compared to conventional PWM inverter. This paper presents the implementation on a field programmable gate array(FPGA) of a SVPWM module for a voltage source inverter. The SVPWM module consists of PWM generator, current and position sensor interface and dead time compensator. The implemented SVPWM module can be integrated with a digital signal processor(DSP) to provide a flexible and effective solution for high performance voltage source inverter and for the use of multi-motor control. The performance of SVPWM module is verified by simulation and several experimental results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.1
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• pp.88-94
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• 2005

This paper presents the design and implementation of a receiver operating between a rotary machine encoder and DSP. The receiver connects with the encoder using 1 bit serial data and DSP using 16 bits bus line. The receiver and encoder use the different operating frequency each other. We suggest a new apparatus and method of synchronized code for header detection in 1bit serial communication. The system operating frequency can be changed into 20MHz or 60MHz by using the external port such as 'clk_select'.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.35-42
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• 2012

This paper is about the implementation of low cost WiMAX remote radio head system with Ethernet instead of optical link. We deployed a simplified frame structure on the data frames transmitted between a basestation and remote radio heads in order to maximize Ethernet link utilization which shows relatively lower maximum throughput compared to that of optical links. In addition, a synchronization mechanism was applied on a basestation and remote radio heads placed on remote sites in order for simultaneous data transmission and reception in all remote radio heads which are essential for proper communication with terminals. These schemes are implemented with FPGA. The results of experiment with a WiMAX Femtocell show that our remote radio head systems efficiently deliver radio frames with proper timing.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.263-266
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• 2012

This paper describes an efficient hardware implementation of Whirlpool hash function as ISO/IEC 10118-3 standard. Optimized timing is achieved by using pipelined small LUTs, and Whirlpool block cipher and key schedule have been implemented in parallel for improving throughput. In key schedule, key addition is area-optimized by using inverters and muxes instead of using rom and xor gates. This hardware has been implemented on Virtex5-XC5VSX50T FPGA device. Its maximum operating frequency is about 151MHz, and throughput is about 950Mbps.

• Journal of Satellite, Information and Communications
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• v.3 no.2
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• pp.38-42
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• 2008

In 2005, DVB-S2 spec. was finalized. But with a large number of DVB-S receivers already installed, backwards compatibility may be required for a period of time, where old receivers continue to receive the same capacity as before, while the new DVB-S2 receivers could receive additional capacity broadcasts. To facilitate the reception of DVB-S serviced by DVB-S2 receivers, implementation of DVB-S in DVB-S2 chips is highly recommended. For the backward compatibility the system adapt the hierarchical modulation scheme. And the system has to meet system margin, so in this paper analyzes the effect according to the deviation angle and shows the BER performance. And finally this paper shows the result of the system implement using FPGA chip.