• 한국수산과학회지
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• 제51권2호
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• pp.178-186
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• 2018

A chirp-echo data acquisition and processing system was developed for use as a simplified, PC-based chirp echo-sounder with some data processing software modules. The design of the software and hardware system was implemented via a field-programmable gate array (FPGA). Digital signal processing algorithms for driving a single-channel chirp transmitter and dual-channel receivers with independent TVG (time varied gain) amplifier modules were incorporated into the FPGA for better real-time performance. The chirp-echo data acquisition and processing system consisted of a notebook PC, an FPGA board, and chirp sonar transmitter and receiver modules, which were constructed using three chirp transducers operating over a frequency range of 35-210 kHz. The functionality of this PC-based chirp echo-sounder was tested in various field experiments. The results of these experiments showed that the developed PC-based chirp echo-sounder could be used in the acquisition, processing and analysis of broadband acoustic echoes related to fish species identification.

• 한국전자파학회논문지
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• 제29권2호
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• pp.138-141
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• 2018

본 논문에서는 FPGA를 이용하여 디지틀 방식으로 영상 레이다에 사용하는 주파수 변조된 첩(Chirp) 신호를 생성하고, 이 신호를 I-Q 변조하여 RF 신호로 변환 한 후 24 주파수 체배기로 체배하여 94 GHz W-대역에서 광대역 첩 신호발생 장치의 설계, 제작한 연구 결과를 제시한다. 개발된 첩 발생기는 94 GHz의 캐리어 주파수와 960 MHz의 대역폭을 가지는 주파수 변조된 신호이며, 평탄도는 IF단(3.9 GHz)에서 1 dB 이내, W-대역에서 2 dB 이내 그리고 3 W의 출력을 보여주고 있다.

• 한국항공우주학회지
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• 제50권2호
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• pp.119-125
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• 2022

본 논문에서는 500kg급 중형위성에 탑재를 목표로 개발한 C-밴드 영상 레이다용 파형발생수신모듈의 설계, 제작 및 시험 결과를 제시한다. 파형발생수신모듈은 약 500km의 고도에서 해상도 10m 기준 120km의 관측 폭을 만족할 수 있도록 50MHz 대역의 2개 주파수를 동시 운용하는 이중주파수 스캔 방식을 적용할 수 있도록 설계하였다. 제작된 파형발생수신모듈은 우주환경을 고려하여 방사성 내성이 고려된 RTG4 FPGA를 적용하였으며, 병렬 직접합성방식(PDDS)을 적용하여 메모리 맵 방식 대비 작은 메모리 용량으로 첩 신호를 생성할 수 있도록 구현하였다. 시험결과 주파수 순도가 높은 첩 파형을 안정적으로 생성하였으며, 수신 신호에 대해 디지털 하향 변환 후 확인 결과 목표한 IRF (Impulse Response Function) 성능을 확인할 수 있었다.

• 한국정보기술응용학회:학술대회논문집
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• 한국정보기술응용학회 2005년도 6th 2005 International Conference on Computers, Communications and System
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• pp.339-342
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• 2005

In order to support ultrawide-band signal generation for low rate WPAN, several types of signal generation mechanisms are suggested such as Chaos, Impluse, and Chirp signals by the activity of IEEE 802.15.4a. The communication system applied chaos theory may have ultrawide-band characteristics with spread spectrum and immunity from multipath effect. In order to use the advantage of chaotic signal generation, we introduce the system implementation of communication and networking systems with the chaos UWB signal. This system may be composed of mainly three parts in hardware architecture : RF transmission with chaotic signal generation, signal receiver using amplifiers and filters, and 8051 & FPGA unit. The most difficult part is to implement the chaotic signal generator and build transceiver with it. The implementation of the system is devidced into two parts i.e. RF blocks and digital blocks with amplifiers, filters, ADC, 8051 processor, and FPGA. In this paper, we introduce the system block diagram for chaotic communications. Mainly the RF block is important for the system to have good performance based on the chaotic signal generator. And the main control board functions for controlling RF blocks, processing Tx and Rx data, and networking in MAC layer.

• 한국군사과학기술학회지
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• 제25권4호
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• pp.347-354
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• 2022

The synthetic aperture radar(SAR) is an equipment that can acquire images in all weathers day and night based on radar signals. The on-board processor of satellite SAR generates transmission signal by digital signal processing, converts it into an analog signal and transmits to antenna. Until the transmission signal generated by on-board processor is output, the signal passes the transmission cables and analog devices. At this time, these hardware distort the signal and makes SAR performance worse. To improve the performance, pre-distortion technique is used. But, general pre-distortion using taylor series is not sufficient to compensate for the distortion. This paper suggests transmit signal design method with improved pre-distortion. This paper uses envelop sampling method and interpolation filter for frequency domain compensation. The proposed method accurately compensates the hardware distortion and reduces resource usage of FPGA. To analyze proposed method's performance, IRF characteristics are compared when the proposed method applies to signal with errors.

• 한국전자파학회논문지
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• 제27권3호
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• pp.326-329
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• 2016

무인항공기는 전투뿐만 아니라, 정찰, 관측 탐사 등 여러 분야에서 이용할 수 있고, 전천후 영상 수집이 가능한 SAR(Synthetic Aperture Radar) 기술과 함께 기존의 감시정찰 체계가 수행할 수 없던 임무영역까지로 그 능력이 확장될 것으로 보인다. 오늘날, 고효율 집적기술의 발전과 시스템 경량화 기술의 발전에 힘입어 무인항공기에도 경량의 SAR Sensor를 탑재하려는 연구와 수요가 증가하고 있다. 이에 따라, 본 논문에서는 SAR 시스템을 구성하는 핵심 모듈인 광대역 첩신호발생기를 DDS 디지털 소자 기반으로 개발하여 무인항공기용 신호 발생기와 송수신장비의 개발과정 및 결과를 기술하였다.

• 한국자동차공학회논문집
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• 제25권1호
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• pp.92-102
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• 2017

For an automotive surveillance radar system, fast-chirp train based FMCW (Frequency Modulated Continuous Wave) radar is a very effective method, because clutter and moving targets are easily separated in a 2D range-velocity map. However, pedestrians with low echo signals may be masked by strong clutter in actual field. To address this problem, we proposed in the previous work a clutter cancellation and moving target indication algorithm using the coherent phase method. In the present paper, we initially composed the test set-up using a 24 GHz FMCW transceiver and a real-time data logging board in order to verify this algorithm. Next, we created two indoor test environments consisting of moving human and stationary targets. It was found that pedestrians and strong clutter could be effectively separated when the proposed method is used. We also designed and implemented these algorithms in FPGA (Field Programmable Gate Array) in order to analyze the hardware and time complexities. The results demonstrated that the complexity overhead was nearly zero compared to when the typical method was used.