• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.359-360
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• 2008

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.65-73
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• 2002

In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

• Speech Sciences
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• v.10 no.2
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• pp.57-64
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• 2003

The cepstrum coefficients are the most popular feature for speech recognition or speaker recognition. The cepstrum coefficients are also used for speech synthesis and speech coding but has major drawback of long processing time. In this paper, we proposed a new method that can reduce the processing time of FFT cepstrum analysis. We use the normal ordered inputs for FFT function and the bit-reversed inputs for IFFT function. Therefore we can omit the bit-reversing process and reduce the processing time of FFT ceptrum analysis.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.1
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• pp.37-41
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• 2014

FFT (Fast Fourier Transform) has been widely used in various fields such as image processing, voice processing, physics, astronomy, applied mathematics and so forth. Much research has been conducted due to the importance of the FFT and recently new FFT algorithms using a GPU (Graphics Processing Unit) have been developed for the purpose of much faster processing. In this paper, the new optimal FFT algorithm using the Pease FFT algorithm has been proposed reflecting the hardware configuration of a GPGPU (General Purpose computing of GPU). According to the experiments, the proposed algorithm outperformed by between 3% to 43% compared to the CUFFT algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2227-2232
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• 2007

In this paper, it is presented a Real FFT for the FMCW radar distance measurement with high resolution. The high distance resolution needs the measurement of the accurate beat frequency. To improve the distance resolution, zoom fft, decimation, digital low pass filter and zero padding method are used. The simulation results using the Matlab show ${\pm}5mm$ of distance resolution and the measuring range is up to 35meter.

• Journal of Broadcast Engineering
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• v.18 no.2
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• pp.204-214
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• 2013

Recently various research have been conducted relating to the implementation of signal processing or communication system by software using the massively parallel processing capability of the GPU. In this work, we focus on reducing software simulation time of 2K/8K FFT in DVB-T by using GPU. we estimate the processing time of the DVB-T system, which is one of the standards for DTV transmission, by CPU. Then we implement the FFT processing by the software using the NVIDIA's massively parallel GPU processor. In this paper we apply stream process method to reduce the overhead for data transfer between CPU and GPU, coalescing method to reduce the global memory access time and data structure design method to maximize the shared memory usage. The results show that our proposed method is approximately 20~30 times as fast as the CPU based FFT processor, and approximately 1.8 times as fast as the CUFFT library (version 2.1) which is provided by the NVIDIA when applied to the DVB-T 2K/8K mode FFT.

• Journal of IKEEE
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• v.16 no.3
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• pp.189-196
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• 2012

This paper proposes new phase error compensation method of RVDT encoder in the FFT domain. Phase errors are measured with a small combination of compensation resistors and the changes of first order coefficients of FFT for each resistor are obtained. It is found that the coefficient change is inversely proportional to the inserted resistor. The proposed method takes less time and the size of the table is smaller than previous time domain approaches. In addition, the location of the compensation resistor can be found through axis transformation of the coefficients. Finally, the peak-to-peak phase error was improved to 0.57 which is two times better than previous one.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.7
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• pp.1024-1031
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• 2012

In this paper, FMCW type radar level transmitter using correlation analysis method is implemented for precise distance measurement of cargo tank. FMCW type radar level transmitter is the device for distance measurement which calculates the distance by analyzing the beat frequency, that is, the frequency difference between Tx and RX signal from radar antenna using Fast Fourier Transform(FFT), but compensated algorithm like Zoom FFT is needed for the improvement of the frequency precision because the frequency precision of FFT is limited depending on sampling frequency and the number of sampling data. In case of Zoom FFT, the number of sampling data and noisy signal are the main factor influencing the measurement accuracy of Zoom FFT like FFT. Therefore, in order to overcome the limited environment and achieve the precise measurement, correlation coefficient is used for the distance measurement and the errors of measurement are verified to be in the range of ${\pm}1mm$.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04d
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• pp.73-75
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• 2003

OFDM 전송방식에 있어서 중요한 주파수 옵셋 추정을 하는데 있어서 기존의 FFT 방법이 가지고 있는 문제점을 보완하는 알고리즘이 많이 연구되고 있다. FFT의 정수배 옵셋외에 소수배 옵셋이 생겼을때 제대로 추정해 낼 수 없는 점을 보완하는 High resolutional technical 알고리즘을 보면 MVDR, MUSIC, root MUSIC, PISARENCO 등이 있다. 본 논문에서는 이러한 알고리즘 중에 MPM(Matrix Pencil Method)를 이용하여 FFT의 문제점을 보완하고 옵셋 추정을 시뮬레이션 해 보았다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.36-42
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• 2010

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically $log_2N$) as the FFT point-size (N) increases, the number of required registers (or, memories) increases linearly. In large point-size FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 38.5% area reduction compared with previous IFFT designs.