• Title/Summary/Keyword: FCSR

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On the Characteristic and Analysis of FCSR Sequences for Linear Complexity (선형복잡도 측면에서 FCSR의 이론절인 특성 및 분석 연구)

  • Seo Chang-Ho;Kim Seok-Woo
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.10
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    • pp.507-511
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    • 2005
  • We have derived the linear complexity of a binary sequence generated by a Feedback with Carry Shift Regiater(FCSR) under the following condition: q is a power of a prime such that $q=r^e,\;(e{\geq}2)$ and r=2p+1, where both r and p are 2-prime. Also, a summation generator creates sequence from addition with carry of LFSR(Linear Feedback Shift Register) sequences. Similarly, it is possible to generate keystream by bitwise exclusive-oring on two FCSR sequences. In this paper, we described the cryptographic properties of a sequence generated by the FCSRs in view of the linear complexity.

A Study on the Cryptographic Properties of FCSR Sequences (FCSR 난수열의 암호학적인 특성에 관한 연구)

  • 서창호;김정녀;조현숙;김석우
    • The KIPS Transactions:PartC
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    • v.8C no.1
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    • pp.12-15
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    • 2001
  • A summation generator creates sequence from addition with carry of LFSR (Linear Feedback Shift Register) sequences. Similarly, it is possible to generate keystream by bitwise exclusive-oring on two FCSR sequences. In this paper, we described the cryptographic properties of a sequence generated by the FCSRs.

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Low Voltage Swing BUS Driver and Interface Analysis for Low Power Consumption (전력소모 감소를 위한 저 전압 BUS 구동과 인터페이스 분석)

  • Lee Ho-Seok;Kim Lee-Sup
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.7
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    • pp.10-16
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    • 1999
  • This paper describes a low voltage swing bus driver using FCSR(Feedback Control Swing voltage Reduction) which can control bus swing voltage within a few hundred of mV. It is proposed to reduce power consumption in On-chip interface, especially for MDL(Merged DRAM Logic) architecture wihich has wide and large capacitance bus. FCSR operates on differential signal dual-line bus and on precharged bus with block controlling fuction. We modeled driver and bus to scale driver size automatically when bus environment is variant. We also modeled coupling capacitance noise(crosstalk) of neighborhood lines which operate on odd mode with parallel current source to analysis crosstalk effect in the victim-line according as voltage transition in the aggressor-line and environment in the victim-line. We built a test chip which was designed to swing 600mV in bus, shows 70Mhz operation at 3.3V, using Hyundai 0.8um CMOS technology. FCSR operate with 250Mhz at 3.3V by Hspice simulation.

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Improvement of Properties of the Fuzzy ART with the Variable Weighed Average Learning (가변 가중 평균 학습을 적용한 퍼지 ART 신경망의 성능 향상)

  • Lee, Chang joo;Son, Byounghee
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.42 no.2
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    • pp.366-373
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    • 2017
  • In this paper, we propose a variable weighted average (VWA) learning method in order to improve the performance of the fuzzy ART neural network that has been developed by Grossberg. In a conventional method, the Fast Commit Slow Recode (FCSR), when an input pattern falls in a category, the representative pattern of the category is updated at a fixed learning rate regardless of the degree of similarity of the input pattern. To resolve this issue, a variable learning method proposes reflecting the distance between the input pattern and the representative pattern to reduce the FCSR's category proliferation issue and improve the pattern recognition rate. However, these methods still suffer from the category proliferation issue and limited pattern recognition rate due to inevitable excessive learning created by use of fuzzy AND. The proposed method applies a weighted average learning scheme that reflects the distance between the input pattern and the representative pattern when updating the representative pattern of a category suppressing excessive learning for a representative pattern. Our simulation results show that the newly proposed variable weighted average learning method (VWA) mitigates the category proliferation problem of a fuzzy ART neural network by suppressing excessive learning of a representative pattern in a noisy environment and significantly improves the pattern recognition rates.

Improvement of Pattern Recognition Capacity of the Fuzzy ART with the Variable Learning (가변 학습을 적용한 퍼지 ART 신경망의 패턴 인식 능력 향상)

  • Lee, Chang Joo;Son, Byounghee;Hong, Hee Sik
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38B no.12
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    • pp.954-961
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    • 2013
  • In this paper, we propose a new learning method using a variable learning to improve pattern recognition in the FCSR(Fast Commit Slow Recode) learning method of the Fuzzy ART. Traditional learning methods have used a fixed learning rate in updating weight vector(representative pattern). In the traditional method, the weight vector will be updated with a fixed learning rate regardless of the degree of similarity of the input pattern and the representative pattern in the category. In this case, the updated weight vector is greatly influenced from the input pattern where it is on the boundary of the category. Thus, in noisy environments, this method has a problem in increasing unnecessary categories and reducing pattern recognition capacity. In the proposed method, the lower similarity between the representative pattern and input pattern is, the lower input pattern contributes for updating weight vector. As a result, this results in suppressing the unnecessary category proliferation and improving pattern recognition capacity of the Fuzzy ART in noisy environments.

Word-Based FCSRs with Fast Software Implementations

  • Lee, Dong-Hoon;Park, Sang-Woo
    • Journal of Communications and Networks
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    • v.13 no.1
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    • pp.1-5
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    • 2011
  • Feedback with carry shift registers (FCSRs) over 2-adic number would be suitable in hardware implementation, but the are not efficient in software implementation since their basic unit (the size of register clls) is 1-bit. In order to improve the efficiency we consider FCSRs over $2^{\ell}$-adic number (i.e., FCSRs with register cells of size ${\ell}$-bit) that produce ${\ell}$ bits at every clocking where ${\ell}$ will be taken as the size of normal words in modern CPUs (e.g., ${\ell}$ = 32). But, it is difficult to deal with the carry that happens when the size of summation results exceeds that of normal words. We may use long variables (declared with 'unsigned _int64' or 'unsigned long long') or conditional operators (such as 'if' statement) to handle the carry, but both the arithmetic operators over long variables and the conditional operators are not efficient comparing with simple arithmetic operators (such as shifts, maskings, xors, modular additions, etc.) over variables of size ${\ell}$-hit. In this paper, we propose some conditions for FCSRs over $2^{\ell}$-adic number which admit fast software implementations using only simple operators. Moreover, we give two implementation examples for the FCSRs. Our simulation result shows that the proposed methods are twice more efficient than usual methods using conditional operators.