• Journal of Navigation and Port Research
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• v.30 no.10 s.116
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• pp.793-800
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• 2006

The purpose of this paper is to show a way for extracting the core input and output variable in Korean seaports by using principal component analysis and DEA(data envelopment analysis). Two inputs(birthing capacity, and cargo handling capacity) and three outputs(export cargo handling amount, import cargo handling amount, and number of ship calls), and three cross sectional data(1995, 2000, and 2004) for 26 Korean seaports are considered for measuring the efficiencies of 21 DEA models. 21 models can be treated as variables and efficiencies as observations for extracting the core inputs and outputs variables by using principal component analysis. An empirical main result indicates that core input variable is cargo handling capacity, and core output is the number of ship calls. The Korean seaport authority can adopt the DEA and principal component analysis for deciding the development and investment to each seaport.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.786-789
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• 2002

A recurrent artificial neural network (ANN) model is developed to simulate hydrocarbon recovery process at petroleum-contaminated site. The groundwater extraction rate, vacuum pressure, and saturation hydraulic conductivity are selected as the input variables, while the cumulative hydrocarbon recovery volume is considered as the output variable. The experimental data fer establishing the ANN model are from implementation of a multiphase flow model for dual phase remediation process under different input variable conditions. The complex nonlinear and dynamic relationship between input and output data sets are then identified through the developed ANN model. Reasonable agreements between modeling results and experimental data are observed, which reveals high effectiveness and efficiency of the neural network approach in modeling complex hydrocarbon recovery behavior.

• International Journal of Control, Automation, and Systems
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• v.4 no.4
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• pp.438-447
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• 2006

Fuzzy controller's design depends mainly on the rule base and membership functions over the controller's input and output ranges. This paper presents two different approaches to deal with these design issues. A simple and efficient approach; namely, Fuzzy Subtractive Clustering is used to identify the rule base needed to realize Fuzzy PI and PD type controllers. This technique provides a mechanism to obtain the reduced rule set covering the whole input/output space as well as membership functions for each input variable. But it is found that some membership functions projected from different clusters have high degree of similarity. The number of membership functions of each input variable is then reduced using a similarity measure. In this paper, the fuzzy subtractive clustering approach is shown to reduce 49 rules to 8 rules and number of membership functions to 4 and 6 for input variables (error and change in error) maintaining almost the same level of performance. Simulation on a wide range of linear and nonlinear processes is carried out and results are compared with fuzzy PI and PD type controllers without clustering in terms of several performance measures such as peak overshoot, settling time, rise time, integral absolute error (IAE) and integral-of-time multiplied absolute error (ITAE) and in each case the proposed schemes shows an identical performance.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1996.10a
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• pp.327-332
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• 1996

Rough Set theory suggested by Pawlak has a property that it can describe the degree of relation between condition and decision attributes of data which don't have linguistic information. In this paper, by using this ability of rough set theory, we define a occupancy degree which is a measure can represent a degree of relational quantity between condition and decision attributes of data table. We also propose a method that can find an optimal fuzzy rule table and membership functions of input and output variables from data without linguistic information and examine the validity of the method by modeling data generated by fuzzy rule.

• 유체기계공업학회:학술대회논문집
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• 2002.12a
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• pp.346-353
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• 2002

The steam generator feedwater flow rate in a nuclear power plant was estimated by means of artificial neural networks with the wavelet analysis for enhanced information extraction. The fouling of venturi meters, used for steam generator feedwater flow rate in pressurized water reactors, may result in unnecessary plant power derating. The backpropagation network was used to generate models of signals for a pressurized water reactor. Multiple-input single-output heteroassociative networks were used for evaluating the feedwater flow rate as a function of a set of related variables. The wavelet was used as a low pass filter eliminating the noise from the raw signals. The results have shown that possible fouling of venturi can be detected by neural networks, and the feedwater flow rate can be predicted as an alternative to existing methods. The research has also indicated that the decomposition of signals by wavelet transform is a powerful approach to signal analysis for denoising.

• The KSFM Journal of Fluid Machinery
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• v.5 no.4 s.17
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• pp.47-53
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• 2002

The steam generator feedwater flow-rate in a nuclear power plant was estimated by means of artificial neural networks with the wavelet analysis for enhanced information extraction. The fouling of venturi meters, used for steam generator feedwater flow-rate in pressurized water reactors, may result in unnecessary plant power derating. The back-propagation network was used to generate models of signals for a pressurized water reactor Multiple-input, single-output hetero-associative networks were used for evaluating the feedwater flow rate as a function of a set of related variables. The wavelet was used as a low pass filter eliminating the noise from the raw signals. The results have shown that possible fouling of venturi can be detected by neural networks, and the feedwater flow-rate can be predicted as an alternative to existing methods. The research has also indicated that the decomposition of signals by wavelet transform is a powerful approach to signal analysis for denoising.

• The Journal of the Korea Contents Association
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• v.18 no.1
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• pp.10-18
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• 2018

This paper presents a method to resynthesize logic of a programmed FPGA from a bitstream file that is a downloaded file for Xilinx FPGA (Field Programmable Gate Array). It focuses on reconfiguring the LUT (Look Up Table) logic. The bitstream data is compared and analyzed considering various situations and various input variables such as composing other logics using the same netlist or synthesizing the same logic at various positions to find a structure of the bitstream. Based on the analyzed bitstream, we construct a truth table of the LUT by implementing various logic for one LUT. The proposed algorithm extracts the logic of the LUT based on the truth table of the generated LUT and the bitstream. The algorithm determines the input and output pins used to implement the logic in the LUT. As a result, we extract a gate level logic from a bitstream file for the targeted Xillinx FPGA.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.