• Title/Summary/Keyword: Eulerian circuit

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A Study on the Built-in Test Circuit Design for Parallel Testing of CAM(Content Addressable Memory) (CAM(Content Addressable Memory)의 병렬테스팅을 위한 Built-in 테스트회로 설계에 관한 연구)

  • 조현묵;박노경;차균현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.6
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    • pp.1038-1045
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    • 1994
  • In this paper, algorithm and built-in test circuit for testing all PSF(Pattern Sensitive Fault) occuring in CAM(Content Addressable Memory) are proposed. That is, built-in test circuit that uses minimum additional circuit without external equipment is designed. Additional circuit consist`s of parallel comparator, error detector, and modified decoder for parallel testing. Besides, the study on eulerian path for effectiv test pattern is carried out simultaneously. Consequently, using proposed algorithm, we can test all contents of CAM with 325+2b(b:number of bits) operations regardless of number of words. The area occupied by test circuit is about 7.5% of total circuit area.

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A Study on the Test Circuit Design and Development of Algorithm for Parallel RAM Testing (RAM의 병렬 테스팅을 위한 알고리듬개발 및 테스트회로 설계에 관한 연구)

  • 조현묵;백경갑;백인천;차균현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.17 no.7
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    • pp.666-676
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    • 1992
  • In this paper, algorithm and testable circuit to find all PSF(Pattern Sensitive Fault ) occured in RAM were proposed. Conventional test circuit and algorithm took much time in testing because consecutive test for RAM cells or f-dimensional memory struciure was not employed. In this paper, methodology for parallel RAM-testing was proposed by compensating additional circuit for test to conventional RAM circuit. Additional circuits are parallel comparator, error detector, group selector circuit and a modified decoder used for parallel testing. And also, the constructive method of Eulerian path to obtain efficient test pattern was performed. Consequently, If algorithm proposed in this paper Is used, the same operations as 32sxwor4 lines will be needed to test b x w=n matrix RAM. Circuit simulation was performerd, and 10 bits x :If words testable RAM was designed.

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A Study on Discrete Mathematics Subjects Focused on the Network Problem for the Mathematically Gifted Students in the Elementary School (초등 영재교육에 적용 가능한 이산수학 주제의 내용 구성에 관한 소고 -네트워크 문제를 중심으로-)

  • Choi, Keun-Bae
    • School Mathematics
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    • v.7 no.4
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    • pp.353-373
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    • 2005
  • The purpose of this paper is to analysis the basic network problem which can be applied to the mathematically gifted students in elementary school. Mainly, we discuss didactic transpositions of the double counting principle, the game of sprouts, Eulerian graph problem, and the minimum connector problem. Here the double counting principle is related to the handshaking lemma; in any graph, the sum of all the vertex-degree is equal to the number of edges. The selection of these subjects are based on the viewpoint; to familiar to graph theory, to raise algorithmic thinking, to apply to the real-world problem. The theoretical background of didactic transpositions of these subjects are based on the Polya's mathematical heuristics and Lakatos's philosophy of mathematics; quasi-empirical, proofs and refutations as a logic of mathematical discovery.

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