• Journal of Institute of Control, Robotics and Systems
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• v.17 no.11
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• pp.1101-1105
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• 2011

Radiation particles can introduce temporary errors in memory systems. To protect against these errors, so-called soft errors, error detection and correcting codes are used. In addition, scrubbing is applied which is a fundamental technique to avoid the accumulation of soft errors. This paper introduces an optimal scrubbing scheme, which is suitable for a system with auto error detection and correction logic. An auto error detection and correction logic can correct soft errors without CPU's writing operation. The proposed scrubbing scheme leads to maximum reliability by considering both allowable scrubbing load and the periodic accesses to memory by the tasks running in the system.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.183-185
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• 1988

Some efficient methods for solving the equations over GF($2^m$) are proposed in this paper. Using these algorithms, parallel decoder for a triple-error-correcting(31, 16) BCH code is implemented. By incorporating with ROM and PAL which are inserted in a decoder, the complex logic circuits can be substantially reduced and therefore a high speed decoder can be constructed.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.59-67
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• 2013

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.75-80
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• 2004

An iterative soft-decision decoding algorithm of block codes is proposed. With careful examinations of the first hard-decision decoding result, the candidate codewords are efficiently searched for. An approach to reducing decoding complexity and lowering error probability is to select a small number of candidate codewords. With high probability, we include the codewords which are at the short distance from the received signal. The decoder then computes the distance to each of the candidate codewords and selects the codeword which is the closest. We can search for the candidate codewords which make the error patterns contain the bits with small reliability values. Also, we can reduce the cases that we select the same candidate codeword already searched for. Computer simulation results are presented for (23,12) Golay code. They show that decoding complexity is considerably reduced and the block error probability is lowered.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.11-15
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• 2015

In this paper, we introduce three modulation codes of the code rate 1/2 with different minimum distances, respectively, and investigate the performance of the codes according to the minimum distance. We simulate the codes in accordance with blur and misalignment. As the minimum distance increases, the complexity of encoder and decoder also grows. However, it can improve the error correcting capability and shows good performance with blur and misalignment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.1A
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• pp.43-50
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• 2012

The use of an error-correcting code is essential in digital communication systems where the channel is noisy. Unless a receiver has accurate channel coding parameters, it becomes difficult to decode the digitized encoding bits correctly. In this paper, estimation algorithm for RM(Reed-Muller) codes using FHT (Fast Hadamard algorithm) is proposed. The proposed algorithm estimates the channel coding parameters of RM codes and then decodes the codes using the characteristic of FHT. And we also verify the algorithm by performing intensive computer simulation in additive white gaussian noise (AWGN) channel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.4
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• pp.324-330
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• 1990

In this paper, the hybrid ARQ system involving the single error correcting and double error detection (127, 119) cyclic Hamming codes and the SR(selective repeat) ARQ schemes with a finite receiver buffer has been designed and constructed. The system performance has been analyzed and simulated. As a result of the simulation, it has been shown that the transmitter retransmitted those data blocks that were detected in errors especially the request signal errors using two retransmission. The system performance was measured by throughput efficiency due to channel error effects.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.677-680
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• 2011

Error detection and correcting codes are typically used to protect against soft errors. In addition, scrubbing is applied which is a fundamental technique to avoid the accumulation of soft errors. This paper introduces an optimal scrubbing scheme, which is suitable for a system with auto error detection and correction logic. An auto error detection and correction logic can correct soft errors without CPU's writing operation. The proposed scrubbing scheme leads to maximum reliability by considering both allowable scrubbing load and the periodic accesses to memory by the tasks running in the system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.329-337
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• 2005

In this paper, we propose a new type of RAKE receiver for complementary code keying (CCK) codes, which is suitable for the multipath channel with large delay spread. Our proposed system is based on channel matched filter (CMF) with decision feedback equalizer (DFE) and contains codeword DFE structure. In our system, inter chip interference (ICI) and inter symbol interference (ISI) generated due to multipath environments are calculated by using detected CCK codeword. Also it uses the error correcting capability of CCK codes, and it can remove ISI and ICI at the same time.

• Journal of the Korea Society of Computer and Information
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• v.5 no.4
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• pp.90-95
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• 2000

In order to enhance the confidence in the mobile communication and improve the performance of the bit error, we have been using coding method. In the case of this, we have to add redundancy bits by using error correcting codes such as the block or convolutional codes. However, the result of redundancy bits causes to improve confidence. but to drop the efficiency in the bandwidth. We have studied coding method that we are able to get the good coding gain without any changes in the data transmission rates in the limited bandwidth. In this Paper, we design TCM(Trellis Coded Modulation) which was proposed by Ungerboeck and MTCM(Multiple TCM), with multiplicity(k＝2), which was proposed by Divsalar, using the optimum encoder. As state number is varied in the optimum encoder, we compare the performance of the TCM and MTCM by using Monte Carlo simulation.