• Smart Media Journal
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• v.13 no.3
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• pp.53-61
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• 2024

This paper presents a novel M-shaped encoder-decoder architecture for skin lesion segmentation, achieving better performance than existing approaches. The proposed architecture utilizes the left and right legs to enable multi-scale feature extraction and is further enhanced by integrating an attention module within the skip connection. The image is partitioned into four distinct patches, facilitating enhanced processing within the encoder-decoder framework. A pivotal aspect of the proposed method is to focus more on critical image features through an attention mechanism, leading to refined segmentation. Experimental results highlight the effectiveness of the proposed approach, demonstrating superior accuracy, precision, and Jaccard Index compared to existing methods

• ETRI Journal
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• v.27 no.5
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• pp.557-562
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• 2005

Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a $0.35 {\mu}m$ CMOS standard cell library.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.431-434
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• 2004

In this paper we present about implementation of channel coder and Viterbi decoder for Mobile communication & IEEE 802.11a Wireless LAN. In the IEEE 802.11a Wireless LAN decoding provided that Viterbi algorithm and convolutional encoder by constraint k=7, ($133_8,\;171_8$) for channel error correction. This Paper presents a novel survivor memory management and decoding techniques with sequential backward state transition control in the trace-back Viterbi decoder, In order to verification we provide to the examples of circuit design and decoding results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.10
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• pp.2563-2578
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• 1996

In this paper, channel error characteristics are investigated to alleviate the channel error propagation problem of the digital TV transmission systems. First, error propagation problems, which are mainly caused by the inter-frame dependancy and variable length coding of the MPEG-2 baseline encoder, are intensively analyzed. Next, existing channel resilient schemes are systematically classified into two kinds of schemes; one for the encoder and the other for the decoder. By comparing the performance and implementation cost, the encoder side schemes, such as error localization, layered coding, error resilience bit stream generation techniques, are described in this paper. Also, in an effort to consider the parcticality of the real transmission situation, an efficient error detection scheme for a decoder system is proposed by employing a priori information of the bit stream syntas, checking the encoding conditions at the encoder stage, and exploiting the statistics of the image itself. Finally, subsequent error concealment technique based on the DCT coefficient recovery algorithm is adopted to evaluate the performance of the proposed error resilience technique. The computer simulation results show that the quality of the received image is significantly improved when the bit error rate is as high as 10$^{-5}$ .

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.24-31
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• 1998

This paper presents a pipeline high-level synthesis tool for designing trace-back systolic array viterbi decoder. It consists of a dta flow graph(DFG) generator and a pipeline data path synthesis tool. First, the DFG of the vitrebi decoder is generated in the from of VHDL netlist. The inputs to the DFG generator are parameters of the convolution encoder. Next, the pipeline scheduling and allocationare performed. The synthesis tool explores the design space efficiently, synthesizes various designs which meet the given constraints, and choose the best one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.4
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• pp.984-995
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• 1996

Data errors according to the various noises caused in the satellite communication links are corrected by the Viterbi decoding algorithm which has extreme error correcting capability. In this paper, we designed and implemented a convolutional encoder and Viterbi decoder ASIC which is used to encode the input data at the transmit side and correct the errors of the received data at the receive side for use in the VSAT communication system. And this chip may be used in any BPSK, QPSK, or OQPSK transmission system. The ambiguity resolver corrects PSK modem ambiguities by delaying, interting, and/or exchanging code symbol to restore their original sequence and polarity. In case of previous decoding system, ambiguity state(AS) of data is resolved by external control logic and extra redundancy data are needed to resolve AS. But, by adopting decoder proposed in this paper, As of data is resolved automatically by internal logic of decoder in case of continuous mode, and by external As line withoug extra redudancy data in burst mode case. So, decoding parts are simple in continuous mode and transmission efficiency is increased in bust mode. The features of this chip are full duplex operation with independent transmit and receive control and clocks, start/stop inputs for use in burst mode systems, loopback function to verify encoder and decoder, and internal or external control to resolve ambinguity state. For verification of the function and performance of a fabricated ASIC chip, we equiped this chip in the Central and Remote Earth Station of VSAT system, and did the performance test using the commerical INTELSAT VII under the real satellite link environmens. The results of test were demonstrated the superiority of performance.

• Journal of Broadcast Engineering
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• v.20 no.1
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• pp.171-182
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• 2015

HEVC can increase the coding efficiency significantly compared with H.264/AVC however it requires much larger computational complexities in both encoder and decoder. In this paper, the decision process of inter-prediction modes in the HEVC reference software has been studied and a fast algorithm to reduce the computational complexity of encoder and decoder is introduced. The proposed scheme introduces a early decision criteria using the outputs of uni-directional predictions to skip the bi-directional prediction estimation. From the experimental results, it was proven that the proposed method can reduce the encoding complexity by 12.0%, 14.6% and 17.2% with 0.6%, 1.0% and 1.5% of coding efficiency penalty, respectively. In addition, the ratio of bi-directional prediction mode was reduced by 6.3%, 11.8% and 16.6% at the same level of coding efficiency penalty, respectively, which should lead to the decoder complexity reduction. Finally, the effects of the proposed scheme are maintained regardless of the use of the early skip decision algorithm which is implemented in the HEVC reference software.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.172-181
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• 2010

In this paper, we propose an adaptive block quantization method. The propose method perfrect reconstructs side information without high complexity in the encoder side, as transmitting motion vectors from a decoder to an encoder side. Also, at the encoder side, residual signals between reconstructed side information and original frame are adaptively quantized to minimize parity bits to be transmitted to the decoder. The proposed method can effectively allocate bits based on bit error rate of side information. Also, we can achieved bit-saving by transmission of parity bits based on the error correction ability of the LDPC channel decoder, because we can know bit error rate and positions of error bit in encoder side. Experimental results show that the proposed algorithm achieves bit-saving by around 66% and delay of feedback channel, compared with the convntional algorithm.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1995.10a
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• pp.1091-1094
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• 1995

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1996.06a
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• pp.570-573
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• 1996