• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.181-186
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• 2015

With the rapid growth of semiconductor technologies, small-sized devices with powerful computing abilities are becoming a reality. As this environment has a limit on power supply, NVM storage that has a high density and low power consumption is preferred to HDD or SSD. However, legacy software layers optimized for HDDs should be revisited. Specifically, as storage performance approaches DRAM performance, existing I/O mechanisms and software configurations should be reassessed. This paper explores the challenges and implications of using NVM storage with a broad range of experiments. We measure the performance of a system with NVM storage emulated by DRAM with proper timing parameters and compare it with that of HDD storage environments under various configurations. Our experimental results show that even with storage as fast as DRAM, the performance gain is not large for read operations as current I/O mechanisms do a good job hiding the slow performance of HDD. To assess the potential benefit of fast storage media, we change various I/O configurations and perform experiments to quantify the effects of existing I/O mechanisms such as buffer caching, read-ahead, synchronous I/O, direct I/O, block I/O, and byte-addressable I/O on systems with NVM storage.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.6
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• pp.153-162
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• 2009

This paper suggests the novel light-weight signal processing algorithm for wireless sensor network applications which needs low computing complexity and power consumption. Exponential average method (EA) is utilized by real time, to process the magnetometer signal which is analyzed to understand the own physical characteristic in time domain. EA provides the robustness about noise, magnetic drift by temperature and interference, furthermore, causes low memory consumption and computing complexity for embedded processor. Hence, optimal parameter of proposal algorithm is extracted by statistical analysis. Using general and precision magnetometer, detection probability over 90% is obtained which restricted by 5% false alarm rate in simulation and using own developed magnetometer H/W, detection probability over 60~70% is obtained under 1~5% false alarm rate in simulation and experiment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1851-1856
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• 2013

An XML is widely used for web services, such as SOAP(Simple Object Access Protocol) and REST (Representational State Transfer), and also de facto standard for representing data. Since the XML parser using DOM(Document Object Model) requires a preprocessing task creating a DOM-tree, and then storing it into memory, embedded systems with limited resources typically employ a streaming XML parser without preprocessing. In this paper, we propose a new architecture for the streaming XML parser using an APSearch(Adaptive Parallel Search) on FPGA(Field Programmable Gate Array). Compared to other approaches, the proposed APSearch parser dramatically reduces overhead on the software side and achieves about 2.55 and 2.96 times improvement in the time needed for an XML parsing. Therefore, our APSearch parser is suitable for systems to speed up XML parsing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.9
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• pp.773-781
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• 2013

The Hough transform for line detection is widely used in many machine vision applications due to its robustness against data loss and distortion. However, it is not appropriate for real-time embedded vision systems, because it has inefficient computation structure and demands a large number of memory accesses. Thus, this paper proposes an improved voting scheme of the Hough transform, and then applies this scheme to a Hough transform hardware architecture so that it can provide real-time performance with less hardware resource. The proposed voting scheme reduces computation overhead of the voting procedure using correlation between adjacent pixels, and improves computational efficiency by increasing reusability of vote values. The proposed hardware architecture, which adopts this improved scheme, maximizes its throughput by computing and storing vote values for many adjacent pixels in parallel. This parallelization for throughput improvement is accomplished with little hardware overhead compared with sequential computation.

• The KIPS Transactions:PartD
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• v.15D no.5
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• pp.609-620
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• 2008

The service handling the map data in the mobile device including navigation, LBS, Telematics, and etc., becomes various. The size of map data which is stored and managed in the mobile device is growing and reaches in several GB. The conventional navigation system has used the read-only PSF (physical storage format) in order to enhance the performance of system by maximum in the mobile device which has limited resources. So though a little part of the map data is changed the whole data must be updated. In general, it takes several ten minutes to write the 2 GB map data to a flash memory of mobile device. Therefore, we have developed the mobile spatial DBMS (database management system) to solve the problem which is that the partial map data couldn't be updated in the conventional navigation system. And we suggest the policy to guarantee the performance of the navigation system which is implemented using the spatial mobile DBMS and verify this by experiment.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.429-438
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• 2001

GPS (Global Positioning System) is the most ideal navigation system which can be used on the earth irrespective of time and weather conditions. GPS has been used for various applications such as construction, survey, environment, communication, intelligent vehicles and airplanes and the needs of GPS are increasing in these days. This paper deals with the design and implementation of the RTOS (Real-Time Operating System) for a GPS navigation computer in the GPS/INS integrated navigation system. The RTOS provides the optimal environment for execution and the base platform to develop GPS application programs. The key facilities supplied by the RTOS developed in this paper are priority-based preemptive scheduling policy, dynamic memory management, intelligent interrupt handling, timers and IPC, etc. We also verify the correct operations of all application tasks of the GPS navigation computer on the RTOS and evaluate the performance by measuring the overhead of using the RTOS services.

• Journal of Convergence for Information Technology
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• v.9 no.10
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• pp.101-107
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• 2019

This paper proposes a method for detecting faults in conveyor systems used for transportation of raw materials needed in the thermal power plant and cement industries. A small drone was designed in consideration of the difficulty in accessing the industrial site and the need to use it in wide industrial site. In order to apply the system to the embedded microprocessor, hardware and algorithms considering limited memory and execution time have been proposed. At this time, the failure determination method measures the peak frequency through the measurement, detects the continuity of the high frequency, and performs the failure diagnosis with the high frequency components of noise. The proposed system consists of experimental environment based on the data obtained from the actual thermal power plant, and it is confirmed that the proposed system is useful by conducting virtual environment experiments with the drone designed system. In the future, further research is needed to improve the drone's flight stability and to improve discrimination performance by using more intelligent methods of fault frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.631-634
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• 2009

Recent advances in wireless communication, electronics, MEMS device, sensor and battery technology have made it possible to manufacture low-cost, low-power, multi-function tiny sensor nodes. A large number of tiny sensor nodes form sensor network through wireless communication. Sensor networks represent a significant improvement over traditional sensors, research on Zigbee wireless image transmission has been a topic in industrial and scientific fields. In this paper, we design a Zigbee wireless image sensor node and multimedia monitoring server system. It consists of embedded processor, memory, CMOS image sensor, image acquisition and processing unit, Zigbee RF module, power supply unit and remote monitoring server system. In the future, we will further improve our Zigbee wireless image sensor node and monitoring server system. Besides, energy-efficient Zigbee wireless image transmission protocol and interworking with mobile network will be our work focus.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.2
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• pp.365-375
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• 2019

A PLC (Programmable Logic Controller) is a highly-reliable industrial digital computer which supports real-time embedded control applications for safety-critical control systems. Real-time operating systems such as uC/OS have been used for PLCs and must meet real-time constraints. As PLCs have been widely used for industrial control systems and connected to the Internet, they have been becoming a main target of cyberattacks. In this paper, we propose an execution code sanitizer to enhance the security of PLC systems. The proposed sanitizer analyzes PLC programs developed by an IDE before downloading the program to a target PLC, and mitigates security vulnerabilities of the program. Our sanitizer can detect vulnerable function calls and illegal memory accesses in development of PLC programs using a database of vulnerable functions as well as the other database of code patterns related to pointer misuses. Based on these DBs, it detects and removes abnormal use patterns of pointer variables and existence of vulnerable functions shown in the call graph of the target executable code. We have implemented the proposed technique and verified its effectiveness through experiments.