• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1226-1227
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• 2008

In this study, a single p-type Si nanowire - Au nanoparticles nano floating gate memory (NFGM) device is successfully fabricated and characterized their memory effects by comparison of electrical characteristics of p-type Si nanowire-based field effect transistor (FET) devices with Au nanoparticles embedded in the $Al_2O_3$ gate materials and without the Au nanoparticles. Drain current versus gate voltage ($I_{DS}-V_{GS}$) characteristics of a single p-type Si nanowire - Au nanoparticle NFGM device show counterclockwise hysteresis loops with the threshold voltage shift of ${\Delta}V_{th}$= 3.0 V. However, p-type Si nanowire based top-gate device without Au nanoparticles does not exhibit a threshold voltage shift. This behavior is ascribed to the presence of the Au nanoparticles, and is indicative of the trapping and emission of electrons in the Au nanoparticles.

• Journal of KIISE:Databases
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• v.35 no.5
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• pp.400-410
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• 2008

Flash memory has been widely used in mobile devices, such as mobile phone and digital camera. Recently flash SSD(Solid State Disk), having same interface of the disk drive, is replacing the hard disk of some laptop computers. However, flash memory still cannot be considered as the storage of database systems. The FTL(Flash Translation Layer) of commercial flash SSD, making flash memory operate exactly same as a hard disk, shows poor performance on the workload of databases with many random overwrites. Recently In-Page Logging(IPL) approach was proposed to solve this problem. In this paper, we implement IPL approach on SQLite, a popular open source embedded DBMS, and evaluate its performance. It improves the performance by up to 30 factors for update queries.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3C
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• pp.286-295
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• 2003

In this paper, the wavelet image coder, that can encode the image to various bit rate with minimum memory usage, is proposed. The proposed coder is used the 2D significant coefficient array(SCA) that has bit level informal on of the wavelet coefficients to reduce the memory requirement in coding process. The 2D SCA is two dimensional data structure that has bit level information of the wavelet coefficients. The proposed algorithm performs the coding of the significance coefficients and coding of bit level information of wavelet coefficients at a time by using the 2D SCA. Experimental results show a better or similar performance of the proposed method when compared with conventional embedded wavelet coding algorithm. Especially, the proposed algorithm performs stably without image distortion at various b it rates with minimum memory usage by using the 2D SCA.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1697-1706
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• 2013

Protocol analyzer is being used to analyze proper processing of CMD & data when developing SD slave IP. In this thesis, a protocol analyzer was developed for analyzing SD protocol in Windows environment using Visual C++. SD protocol analyzer consists of embedded Linux software for storing SD memory data and MFC program for analyzing this. As for protocol analysis, it has been designed to collect data transmitted from SD memory card to host by Linux software for its analysis by MFC. It was found through the experiment that the CMD type could be confirmed that occurs when reading and writing data to SD memory card using the developed board, and debugging the problems that occur was possible.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.136-137
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• 2007

In this study, a single ZnO nanowire - CdTe nanoparticle nano floating gate memory (NFGM) device is successfully fabricated and characterized their memory effects by comparison of electrical characteristics of ZnO nanowire-based field effect transistor (FET) devices with CdTe nanoparticles embedded in the $Al_2O_3$ gate materials and without the CdTe nanoparticles.

• Journal of the Semiconductor & Display Technology
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• v.23 no.3
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• pp.7-13
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• 2024

With the development of technologies such as the Internet of Things (IoT) and autonomous vehicles, research is being conducted on embedded processors that meet high performance, low power, and memory efficiency. The "C" expansion of the RISC-V processor is required to increase memory efficiency. In this paper, we propose an RV32IC processor and compare the benchmark performance score of the RV32I processor with the code size generated by the GCC compiler. In addition, we propose memory access and combination methods to support 16-bit compression commands, and command extension methods. The proposed RV32IC processor satisfies the maximum operating frequency of 50 MHz on the Artix-7 FPGA. The performance was checked using the benchmark programs of the Dhrystone and Coremark, and the code sizes of the RV32I and RV32IC generated by the GCC compiler were compared. The proposed processor RV32IC decreased DMIPS/MHz by 2.72% and Coremark/MHz by 0.61% compared to RV32I, but Coremark's code size decreased by 14.93%.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.476-487
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• 2007

Flash memory offers attractive features, such as non-volatile, shock resistance, fast access, and low power consumption for data storage. However, it has one main drawback of requiring an erase before updating the contents. Furthermore, flash memory can only be erased limited number of times. To overcome limitations, flash memory needs a software layer called flash translation layer (FTL). The basic function of FTL is to translate the logical address from the file system like file allocation table (FAT) to the physical address in flash memory. In this paper, a new FTL algorithm called an efficient and advanced space-management technique (EAST) is proposed. EAST improves the performance by optimizing the number of log blocks, by applying the state transition, and by using reallocation blocks. The results of experiments show that EAST outperforms FAST, which is an enhanced log block scheme, particularly when the usage of flash memory is not full.

• KIISE Transactions on Computing Practices
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• v.20 no.9
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• pp.519-524
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• 2014

The operating systems in the system architecture, which is integrated several applications and modular electronic devices in the same computing device, demand partitioning technology for safety. Thus, operation system requires partition scheduler for partition scheduling. When we design partition scheduler in embedded system, which has small memory and low performance, such as space system, we must consider not only performance but also memory. In this paper, we introduces a linux-based memory efficient partition scheduler using partition bitmap. This partition scheduler demands small memory space and produce low partition switching overhead. The prototype was executed on a LEON4 processor, which is the Next Generation Multicore Processor (NGMP) in the space sector. In evaluation, this prototype shows accuracy, additional memory space and low partition switching overhead.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.114-124
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• 2014

HEVC is a state-of-the-art video coding standard developed by JCT-VC. HEVC provides about 2 times higher subjective coding efficiency than H.264/AVC. One of the main goal of HEVC development is to efficiently coding UHD resolution video so that HEVC is expected to be widely used for coding UHD resolution video. Decoding such high resolution video generates a large number of memory accesses, so a decoding system needs high-bandwidth for memory system and/or internal communication architecture. In order to determine such requirements, this paper presents an analysis of the memory access complexity for HEVC decoder. we first estimate the amount of memory access performed by software HEVC decoder on an embedded system and a desktop computer. Then, we present the memory bandwidth models for HEVC decoder by analyzing the data flow of HEVC decoding tools. Experimental results show the software decoder produce 6.9-40.5 GB/s of DRAM accesses. also, the analysis reveals the hardware decoder requires 2.4 GB/s of DRAM bandwidth.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.11
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• pp.914-920
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• 2000

When the charge-trap type SONOS(polysilicon-oxide-nitride-oxide-semiconductor) cells are used to flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM(Nonvolatile Semiconductor Memory) cells were fabricated using 0.35 ㎛ standard memory cell embedded logic process including the ONO cell process, based on retrograde twin-well, single-poly, single metal CMOS(Complementary Metal Oxide Semiconductor) process. The thickness of ONO triple-dielectric for the memory cell is tunnel oxide of 24 $\AA$, nitride of 74 $\AA$, blocking oxide of 25 $\AA$, respectively. The program mode(V$\_$g/=7, 8, 9 V, V$\_$s/=V$\_$d/=-3 V, V$\_$b/=floating) and the erase mode(V$\_$g/=-4, -5, -6 V, V$\_$s/=V$\_$d/=floating, V$\_$b/=3 V) by MFN(Modified Fowler-Nordheim) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation(ΔV$\_$th/, S, G$\_$m/) characteristics than channel MFN tunneling operation. Also, the program inhibit conditins of unselected cell for separated source lines NOR-type flash memory application were investigated. we demonstrated that the phenomenon of the program disturb did not occur at source/drain voltage of 1 V∼12 V and gate voltage of -8 V∼4 V.