• Title/Summary/Keyword: Embedded CPU

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Implementation of Memory Copy Reduction Scheme for Multimedia Service in Embedded Linux Kernel (내장형 리눅스 커널에서 멀티미디어 서비스를 위한 메모리 복사 감소 기법의 구현)

  • Kim, Jeong-Won
    • Journal of Korea Multimedia Society
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    • v.7 no.8
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    • pp.1058-1065
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    • 2004
  • Embedded system is widely used in various applications from simple monitor to a set-top box with CPU, memory and hard disk drives. Specially, embedded OS is ported in moveable or small machinery since it ordinarily transmits multimedia data. In this paper, we propose Null copy scheme on the embedded linux system for multimedia service, which can reduce memory copy overhead from user address space to kernel one, and vice versa. Since embedded system for networked multimedia service has low level computing power as well as memory, the Null copy scheme can provide more improved QoS. Our image transmission experiment results on embedded linux target board(CPU utilization an Deadline miss rates) installed a web camera have shown that the proposed scheme can increase fast response and lower CPU overhead.

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An Improving Method of Android Boot Speed in Multi-core based Embedded System (멀티코어 기반의 임베디드 시스템에서 안드로이드 부팅 속도 향상 방법)

  • Choi, Jin-Yong;Lee, Jae-Heung
    • Journal of IKEEE
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    • v.17 no.4
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    • pp.564-569
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    • 2013
  • The current embedded devices are growing rapidly in the multi-core, and these demand fast boot time. But method of previous boot uses core only one. The method includes parallel techniques and modification of CPU Frequency policy. Parallel methods, after analyzing the Android boot process with analysis tool, applied to location where a lot of CPU operation. CPU Frequency policy is modified for high performance of core. The proposed method was applied to S5PV310 dual core and Exynos4412 quad core embedded system. As a result of the experiment, we found that the proposed method makes boot time fast about 20.71% and 31.34% in dual core and quad core environment as compared with the previous method.

Implementation and Performance Evaluation of the Faddev-Leverrier Algorithm using GPGPU (GPGPU를 이용한 파데브-레브리어 알고리즘 구현 및 성능 분석)

  • Park, Yong-Hun;Kim, Cheol-Hong;Kim, Jong-Myon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.8 no.3
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    • pp.171-178
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    • 2013
  • In this paper, we implement the Faddev-Leverier algorithm using GPGPU (General-Purpose Graphics Processing Unit) to accelerate singular value decomposition. In addition, we compare the performance of the algorithm using CPU and CPU plus GPGPU for eleven ${\times}n$ matrix sizes in order to decompose singular values, where =4, 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048, and 4,096. Experimental results indicate that CPU achieves better performance than CPU plus GPGPU for $n{\leq}64$ because of a large number of read and write operations between CPU and GPGPU. However, CPU plus GPGPU outperforms CPU exponentially in the execution time for $n{\geq}64$.

Development of Stand-alone Image Processing Module on ARM CPU Employing Linux OS. (리눅스 OS를 이용한 ARM CPU 기반 독립형 영상처리모듈 개발)

  • Lee, Seok;Moon, Seung-Bin
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.40 no.2
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    • pp.38-44
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    • 2003
  • This paper describes the development of stand-alone image processing module on Strong Arm CPU employing an embedded Linux. Stand-alone image Processing module performs various functions such as thresholding, edge detection, and image enhancement of a raw image data in real time. The comparison of execution time between similar PC and developed module shows the satisfactory results. This Paper provides the possibility of applying embedded Linux successfully in industrial devices.

Embedded Operating System using the Single Address Space(SAS) Architecture (Single Address Space(SAS) Architecture를 이용한 Embedded Operating System)

  • An, Gwang-Hyeok
    • Proceedings of the KIEE Conference
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    • 2003.11c
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    • pp.608-611
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    • 2003
  • A large part of the embedded system, compared with the PC, have low performance CPU and small memory. So the embedded operating system fits the condition of that hardware system. A Single Address Space (SAS) OS has the operating system and all applications in the single address space. The SAS architecture enhances sharing and co-operation, because addresses have a unique interpretation. Thus, pointer-based date structures can be directly communicated and shared between programs at any time, and can be stored directly on storage. The key point of the SAS OS on the embedded system is the low overhead inter-action between programs in process and usage. So SAS OS can be ported on the low performance CPU. In this paper, we design the SAS OS (named emNOS, Embedded Network Operating System) on the ARMTTDMI processor. Finally we show the benefits of the SAS OS on the embedded system.

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The CPU power management technique in the Mobile Embedded System (Mobile 임베디드 시스템의 CPU 소모전력 관리 기법)

  • Kim, Wha-Young;Kim, Young-Kil
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.1
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    • pp.170-176
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    • 2009
  • The efficiently power management is an important requirement traditionally in the mobile communication system which uses battery as their power source. Especially, it has been emphasized in the most devices, which has to provide high performance and various functions with an extended operating time. In this article, the adaptive power management technique for the core CPU unit in Embedded systems used widely for the mobile system thanks to its advantage on power consumption and physical size, is proposed.

A Deadline_driven CPU Power Consumption Management Scheme of the TMO-eCos Real-Time Embedded OS (실시간 임베디드 운영체제 TMO-eCos의 데드라인 기반 CPU 소비 전력 관리)

  • Park, Jeong-Hwa;Kim, Jung-Guk
    • Journal of KIISE:Computing Practices and Letters
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    • v.15 no.4
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    • pp.304-308
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    • 2009
  • This paper presents the deadline driven CPU-Power management scheme for the Real-Time Embedded OS: named TMO-eCos. It used the scheduling scenarios generated by a task serialization technique for hard real- time TMO system. The serializer does a off-line analysis at design time with period, deadline and WCET of periodic tasks. Finally, TMO-eCos kernel controls the CPU speed to save the power consumption under the condition that periodic tasks do not violate deadlines. As a result, the system shows a reasonable amount of power saving. This paper presents all of these processes and test results.

Designing a Embedded System for Remote Control of LDM (LDM 원격 제어를 위한 임베디드 시스템 구성)

  • Moon Cheol-Hong;Kang Sang-Woo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.8 s.338
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    • pp.27-34
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    • 2005
  • In this paper, FPGA It/w and S/W Embedded system for LDM remote control is implemented. XScale CPU is used on developed system and in communcation ethenet and serial is used. CPU interface with H/W LDM rotation and to drive LDM FPGA logic is implemented, to transmit LDM data from long distance command packet is composed, for S/W Embedded linux is used to design linux device driver and linux application program. This S/W is run by module so by loading this module to linu)( file system it can do any movement. Also by compiling Embedded linux to the system it can lower the price of the system. By using this H/W and S/W theory it can be used on any other embedded system.

Design and Implementation of A Dual CPU Based Embedded Web Camera Streaming Server (Dual CPU 기반 임베디드 웹 카메라 스트리밍 서버의 설계 및 구현)

  • 홍진기;문종려;백승걸;정선태
    • Proceedings of the IEEK Conference
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    • 2003.11a
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    • pp.417-420
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    • 2003
  • Most Embedded Web Camera Server products currently deployed on the market adopt JPEG for compression of video data continuously acquired from the cameras. However, JPEG does not efficiently compress the continuous video stream, and is not appropriate for the Internet where the transmission bandwidth is not guaranteed. In our previous work, we presented the result of designing and implementing an embedded web camera streaming server using MPEG4 codec. But the server in our previous work did not show good performance since one CPU had to both compress and process the network transmission. In this paper, we present our efforts to improve our previous result by using dual CPUs, where DSP is employed for data compression and StrongARM is used for network processing. Better performance has been observed, but it is found that still more time is needed to optimize the performance.

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Design of Cache Memory System for Next Generation CPU (차세대 CPU를 위한 캐시 메모리 시스템 설계)

  • Jo, Ok-Rae;Lee, Jung-Hoon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.11 no.6
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    • pp.353-359
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    • 2016
  • In this paper, we propose a high performance L1 cache structure for the high clock CPU. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to reduce miss ratio, and a way-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is stored into the two-way set associative buffer. For the high performance and fast access time, we propose an one way among two ways set associative buffer is selectively accessed based on the way-select table (WST). According to simulation results, access time can be reduced by about 7% and 40% comparing with a direct cache and Intel i7-6700 with two times more space respectively.