• Journal of Power Electronics
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• 제12권4호
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• pp.548-558
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• 2012

In this paper, a novel offset-based single-state pulse width modulation (PWM) method for achieving zero common-mode voltage (CMV) and reducing switching losses in multilevel inverters is presented. The specific active switching state of the zero common-mode (ZCM) voltage that approximates the reference voltage can be deduced from the switching state sequence of the reduced CMV phase disposition PWM (CMV PD PWM) method. From the reference leg voltages for the zero common-mode voltage, an N-to-2-level transformation defines a virtual two-level inverter and the corresponding nominal leg voltage references. The commutation process of the reduced CMV PD PWM method in a multilevel inverter and its outputs can be simply followed in a nominal switching time diagram for the virtual inverter. The characteristics of the reduced CMV PD PWM and the single-state PWM for zero common-mode voltage are analyzed in detail in this paper. The theoretical analysis of the proposed PWM method is verified by experimental results.

• 전력전자학회논문지
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• 제14권4호
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• pp.285-292
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• 2009

본 논문은 다이오드 정류기와 Z-소스 인버터로 교류전동기 구동 시 암 단락 (shoot-through) 상태와 비 암 단락 상태를 나누어 각각 등가회로를 구성하고 공통모드 전압을 분석한다. 음의 값의 공통모드 전압을 감소시키기 위하여 암 단락 시간 제어와 함께 영전압 벡터인가 구간을 제거하는 변형 공간벡터변조기법을 제시한다. PSIM과 32-비트 DSP를 사용한 실험 및 시뮬레이션 결과를 통하여 음의 공통모드전압이 50%이상 감소됨을 확인하였다.

• 전력전자학회논문지
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• 제20권6호
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• pp.509-516
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• 2015

The overmodulation characteristics of a carrier-based medium vector pulse width modulation (CBMVPWM) are examined in this study. CBMVPWM can completely eliminate leakage currents in a three-phase, three-level inverter using only the switching states with the same common mode voltage even in an overmodulation operation. The analytic equations for the magnitude of the output voltage and the switching frequency are derived for overmodulation operation, and the effect of dead time on the leakage current is demonstrated. This study presents the operating principle of CBMVPWM, basic overmodulation features, and simulations and experiments for operating verification.

• Journal of Power Electronics
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• 제17권1호
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• pp.88-95
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• 2017

To reduce common-mode voltage (CMV), various reduced CMV pulse width modulation (RCMV-PWM) algorithms have been proposed, including active zero state PWM (AZSPWM) algorithms, remote state PWM (RSPWM) algorithms, and near state PWM (NSPWM) algorithms. Among these algorithms, AZSPWM algorithms can reduce CMV, but they increase the number of switchings compared to the conventional space vector PWM (CSVPWM). This paper presents a new AZSPWM algorithm for reductions in both the CMV and total number of switchings in BLAC motor drives. Since the proposed AZSPWM algorithm uses only active voltage vectors for motor control, it reduces CMV by 1/3 compared to CSVPWM. The proposed AZSPWM algorithm also reduces the total number of switchings compared to existing AZSPWM algorithms by eliminating the switchings required from one sector to the next. The performance of the proposed algorithm is verified by analyses, simulations, and experimental results.

• Journal of Power Electronics
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• 제18권1호
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• pp.70-80
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• 2018

A novel strategy based on a zero common mode voltage pulse-width modulation (ZCMV-PWM) technique and zero-sequence circulating current (ZSCC) feedback control is proposed in this study to eliminate ZSCCs between three-level neutral point clamped (NPC) voltage source inverters, with common AC and DC buses, that are operating in parallel. First, an equivalent model of ZSCC in a three-phase three-level NPC inverter paralleled system is developed. Second, on the basis of the analysis of the excitation source of ZSCCs, i.e., the difference in common mode voltages (CMVs) between paralleled inverters, the ZCMV-PWM method is presented to reduce CMVs, and a simple electric circuit is adopted to control ZSCCs and neutral point potential. Finally, simulation and experiment are conducted to illustrate effectiveness of the proposed strategy. Results show that ZSCCs between paralleled inverters can be eliminated effectively under steady and dynamic states. Moreover, the proposed strategy exhibits the advantage of not requiring carrier synchronization. It can be utilized in inverters with different types of filter.

• 한국정보전자통신기술학회논문지
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• 제13권3호
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• pp.184-196
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• 2020

본 논문에서는 배터리 관리 시스템 (BMS)에서 2차 전지 배터리를 통해 흐르는 전류의 정밀한 측정을 위한 cascaded-of-integrator feedforward (CIFF) 구조의 단일 비트 2차 델타-시그마 모듈레이터를 제안하였다. 제안된 모듈레이터는 2개의 스위치드 커패시터 적분기, 단일 비트 비교기, 비중첩 클록 발생기 및 바이어스와 같은 주변 회로로 구현하였다. 제안된 구조는 낮은 공통 모드 입력 전압을 가지는 low-side 전류 측정 방법에 적용되도록 설계되었다. Low-side 전류 측정 방법을 사용하면 회로 설계에 부담이 줄어들게 되는 장점을 가진다. 그리고 ±30mV 입력 전압을 15비트 해상도를 가지는 ADC로 분해하기 때문에 추가적인 programmable gain amplifier (PGA)를 구현할 필요가 없어 수 mW의 전력소모를 줄일 수 있다. 제안된 단일 비트 2차 CIFF 델타-시그마 모듈레이터는 350nm CMOS 공정으로 구현하였으며 5kHz 대역폭에 대해 400의 oversampling ratio (OSR)로 95.46dB의 signal-to-noise-and-distortion ratio (SNDR), 96.01dB의 spurious-free dynamic range (SFDR) 및 15.56비트의 effective-number-of-bits (ENOB)을 달성하였다. 델타 시그마 모듈레이터의 면적 및 전력 소비는 각각 670×490㎛2 및 414㎼이다.