• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.183-184
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• 2007

A 40 Gb/s transimpedance amplifier IC was designed and fabricated with a InP/InGaAs HBTs technology. In this study, we interconnect 40Gbps trans impedance amplifier IC to a duroid substrate by a flip chip bonding instead of conventional wire bonding for interconnection. For flip chip bonding, we developed fine pitch bump with the $70{\mu}m$ diameter and $150{\mu}m$ pitch using WLP process. To study the effect of WLP, electrical performance was measured and analyzed in wafer and package module using WLP. The Small signal gains in wafer and package module were 7.24 dB and 6.93dB respectively. The difference of small signal gain in wafer and package module was 0.3dB. This small difference of gain is due to the short interconnection length by bump. The characteristics of return loss was under -10dB in both wafer and module. So, WLP process can be used for millimeter wave GaAs MMIC with the fine pitch pad and duroid substrate can be used in flip chip bonding process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.6
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• pp.556-561
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• 2022

Computational material science as an application of Density Functional Theory (DFT) to the discipline of material science has emerged and applied to the research and development of energy materials and electronic materials such as semiconductor. However, there are a few difficulties, such as generating input files for various types of materials in both the same calculating condition and appropriate parameters, which is essential in comparing results of DFT calculation in the right way. In this tutorial status report, we will introduce how to create crystal structures and to prepare input files automatically for the Vienna Ab initio Simulation Package (VASP) and Gaussian, the most popular DFT calculation programs. We anticipate this tutorial makes DFT calculation easier for the ones who are not experts on DFT programs.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• Korean Journal of Metals and Materials
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• v.46 no.2
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• pp.80-87
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• 2008

Many researches related to the reliability of Pb-free solder joints with PCB (printed circuit board) surface finish under thermal or vibration stresses are in progress, because the electronics is operating in hash environment. Therefore, it is necessary to assess Pb-free solder joints life with PCB surface finish under thermal and mechanical stresses. We have investigated 4-points bending fatigue lifetime of Pb-free solder joints with OSP (organic solderability preservative) and ENIG (electroless nickel and immersion gold) surface finish. To predict the bending fatigue life of Sn-3.0Ag-0.5Cu solder joints, we use the test coupons mounted 192 BGA (ball grid array) package to be added the thermal stress by conducting thermal shock test, 500, 1,000, 1,500 and 2,000 cycles, respectively. An 4-point bending test is performed in force controlling mode. It is considered that as a failure when the resistance of daisy-chain circuit of test coupons reaches more than $1,000{\Omega}$. Finally, we obtained the solder joints fatigue life with OSP and ENIG surface finish using by Weibull probability distribution.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.873-879
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• 2007

We have implemented a highly efficient 2.14-GHz class-F amplifier using Freescale 4-W peak envelope power(PEP) RF Si lateral diffusion metal-oxide-semiconductor field effect transistor(LDMOSFET). Because the control of the all harmonic contents is very difficult, we have managed only the $2^{nd}\;and\;3^{rd}$ harmonics to obtain the high efficiency with simple harmonic control circuit. In order to design the harmonic control circuit accurately, we extracted the bonding wire inductance and drain-source capacitance which are dominant parasitic and package effect components of the device. And then, we have fabricated the class-F amplifier. The measured drain and power-added efficiency are 65.1 % and 60,3 %, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.3
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• pp.15-22
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• 2019

In these days, importance of the power electronic devices and modules keeps increasing due to electric vehicles and energy saving requirements. However, current silicon-based power devices showed several limitations. Therefore, wide band gap (WBG) semiconductors such as SiC, GaN, and $Ga_2O_3$ have been developed to replace the silicon power devices. WBG devices show superior performances in terms of device operation in harsh environments such as higher temperatures, voltages and switching speed than silicon-based technology. In power devices, the reliability of the devices and module package is the critically important to guarantee the normal operation and lifetime of the devices. In this paper, we reviewed the recent trends of the power devices based on WBG semiconductors as well as expected future technology. We also presented an overview of the recent package module and fabrication technologies such as direct bonded copper and active metal brazing technology. In addition, the recent heat management technologies of the power modules, which should be improved due to the increased power density in high temperature environments, are described.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.218-221
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• 2004

The electronic state of ZnO doped with Al, Ga and In, which belong to III family elements in periodic table, was calculated using the density functional theory. In this study, the program used for the calculation on theoretical structures of ZnO and doped ZnO was Vienna Ab-initio Simulation Package (VASP), which is a sort of pseudo potential method. The detail of electronic structure was obtained by the describe variational $X{\alpha}(DV-X{\alpha})$(DV-Xa) method, which is a sort of molecular orbital full potential method. The optimized crystal structures obtained by calculations were compared to the measured structure. The density of state and energy levels of dopant elements was shown and discussed in association with properties.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.7-13
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• 2002

BSCT 320${\times}$240 IRFPA detector module is implemented, which is a key component in uncooled thermal imaging systems. The detector module consists of two parts, infrared sensitive pixel array and read-out integrated circuit(ROIC). The BSCT 320${\times}$240 pixels are made by laser scribe process and 10-${\mu}m$ micro-bump to satisfy 50-${\mu}m$ pitch and 95-% fill-factor. The ROIC has been designed to electrically address the pixels sequentailly and to improve signal-to-noise ratio with single transistor amplifier, HPF, tunable LPF and clamp circuit. The fabricated hybrid chip of detector and ROIC has been mounted on the TEC built-in ceramic package for more stable operation and tested for lots of electrical and optical properties. The IRFA sample has shown successful properties and met with good results of fill-factor, detectivity and responsivity.

• Journal of Welding and Joining
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• v.22 no.1
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• pp.65-70
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• 2004

A soldering process with longitudinal ultrasonic is conducted in this work using the Au bump and substrate. Localized heating of the solder is achieved and the stirring action due to the ultrasonic is found to influence the bond strength and microstructure of the eutectic solder The acceptable bonding condition is determined from the tensile strength. Since the multiple bonds can be formed simultaneously with localized heating, the proposed ultrasonic soldering method appears to be applicable to the high-density electronic package.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1724-1729
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• 2007

Smaller size and higher integration of electronic systems make narrower interconnect pitch not only in chip-level but also in package-level. Moreover electronic systems are required to operate in harsher conditions, that is, higher current / voltage, elevated temperature/humidity, and complex chemical contaminants. Under these severe circumstances, electronic components respond to applied voltages by electrochemically ionization of metals and conducting filament forms between anode and cathode across a nonmetallic medium. This phenomenon is called as the Electrochemical migration