• The Journal of the Korea institute of electronic communication sciences
• /
• v.15 no.3
• /
• pp.413-420
• /
• 2020

The Tactical Information and Communication Network system provides real-time multimedia services such as voice and data by utilizing the Mobile Subscriber Access Point. At this time, an external transmission path is constructed through the Low Capacity Trunk Radio and the High Capacity Trunk Radio system. The communication devices of each wireless transmission system are mounted on a tactical vehicle and a secondary battery is used to prevent a power interruption when the supply power to the tactical vehicle is transferred to the integrated power control device. In this paper, the basic design of the Wireless Power Transfer device for charging the battery of the integrated power control system of the mobile base station system using the Loading Distribution Method and checking the number of primary windings and the core material selection by the air gap through the Finite Elements Method.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.15 no.3
• /
• pp.479-486
• /
• 2020

In this paper, we present a design method for improving the linearity and dynamic range of the analog current mode multiplier circuit, which is one of the key devices in an analog current mode AI processor. The proposed circuit consists of 4 quadrant translinear loops made up of NMOS transistors only, which minimizes physical mismatches of the transistors. The proposed circuit can be implemented at 117㎛ × 109㎛ in 0.35㎛ CMOS process and has a total harmonic distortion of 0.3%. The proposed analog current mode multiplier is expected to be useful as the core circuit of a current mode AI processor.

• Korean Chemical Engineering Research
• /
• v.46 no.3
• /
• pp.465-472
• /
• 2008

Fabrication of nanostructured materials and synthesis of nanomaterials have intensively studied to realize electronic devices for nanotechnology. By using nanoporous alumina mask, nanostructured material can be fabricated in the form of uniform array. The size and the density of the nanostructured materials can be controllable by changing the pore diameter and the density of the alumina mask. This method is possible low cost and on large scale process, and feasible to contribute the fusion technology consisting of information technology, nanotechnology, and biotechnology. Therefore, these techniques provide alternative approaches for development of new electronic applications. In this paper, the fabrication technique and its applications of nanoporous alumina mask are described and nanostructured materials such as quantum dots, nanoholes, and nanorods are introduced.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.23 no.6
• /
• pp.1181-1190
• /
• 2013

The GOOSE(Generic Object Oriented Substation Event) is used as a network protocol to communicate between IEDs(Intelligent Electronic Devices) in international standard IEC 61850 of substation automation system. Nevertheless, the GOOSE protocol is facing many similar threats used in TCP/IP protocol due to ethernet-based operation. In this paper, we develop a IDS(Intrusion Detection System) for secure GOOSE Protocol using open software-based IDS Snort. In this IDS, two security functions for keyword search and DoS attack detection are implemented through improvement of decoding and preprocessing component modules. And we also implement the GOOSE IDS and verify its accuracy using GOOSE packet generation and communication experiment.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.05a
• /
• pp.125-128
• /
• 2011

This paper describes an efficient hardware implementation of HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a $0.35-{\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07a
• /
• pp.62-66
• /
• 2002

The conventional floating zone(FZ) crystal and Czochralski(CZ) silicon crystal have resistivity variations longitudinally as well as radially The resistivity variations of the conventional FZ and CZ crystal are not conformed to requirement of dopant distribution for power devices and thyristors. These resistivity variations in conventional cystals limits the reverse breakdown voltage that could be achieved and forced designers of high power diodes and thyristors to compromise the desired current-voltage characteristics. So to produce high Power diodes and thyristors, Neutron Transmutation Doping(NTD) technique is the one method just because NTD silicon provides very homogeneous distribution of doping concentration. This procedure involves the nuclear transmutation of silicon to phosphorus by bombardment of neutron to the crystal according to the reaction $^{30}$ Si(n,${\gamma}$)longrightarrow$^{31}$ Silongrightarrow(2.6 hr)$^{31}$ P+$\beta$$^{[-10]}$ . The radioactive isotope $^{31}$ Si is formed by $^{31}$ Si capturing a neutron, which then decays into the stable $^{31}$ P isotope (i.e., the donor atom), whose distribution is not dependent on the crystal growth parameters. In this research, neutron was irradiated on FZ silicon wafers which had high resistivity(1000~2000 Ω cm), for 26 and 8.3hours for samples of HTS-1 and HTS-2, and 13, 3.2, 2.0 hours for samples of IP-1, IP-2 and IP-3, respectively, to compare resistivity changes due to time differences. The designed resistivities were approached, which were 2.l Ωcm for HTS-1, 7.21 Ω cm for HTS-2, 1.792cm for IP-1, 6.83 Ωcm for IP-2, 9.23 Ωcm for IP-3, respectively. Point defects were investigated with Deep Level Transient Spectroscopy(DLTS). Four different defects were observed at 80K, 125K, 230K, and above 300K.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.14 no.2
• /
• pp.104-110
• /
• 2001

Structural, optical and electrical properties of Cd$_{1-x}$ Zn$_{x}$S films deposited by chemical bath deposition(CBD), which is a very attractive method for low-cost and large-area solar cells, are presented. Especially, in order to control more effectively the zinc component of the films, zinc acetate, which was used as the zinc source, was added in the reaction solution after preheating the reaction solution and the pH of the reaction solution decreased with increasing the concentration of zinc acetate. The films prepared after preheating and pH control had larger zinc component and higher optical band gap. The crystal structures of Cd$_{1-x}$ Zn$_{x}$S films was a wurtzite type with a preferential orientation of the (002) plane and the lattice constants of the films changed from the value for CdS to those for ZnS with increasing the mole ratio of the zinc acetate. The minimum lattice mismatch between Cd$_{1-x}$ Zn$_{x}$S and CdTe were 2.7% at the mole ratio of (ZnAc$_2$)/(CdAc$_2$+ZnAc$_2$)=0.4. As the more zinc substituted for Cd in the films, the optical transmittance improved, while the absorption edge shifted toward a shorterwavelength. the photoconductivity of the films was higher than the dark conductivity, while the ratio of those increased with increasing the mole ratio of zinc acetate. acetate.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.8
• /
• pp.875-881
• /
• 2004

Fundamental results obtained from an atomic force microscope (AFM) chemically-induced direct nano-lithography process are presented, which is regarded as a simple method for fabrication nm-scale devices such as superconducting flux flow transistors (SFFTs) and single electron tunneling transistors (SETs). Si cantilevers with Pt coating and with 30 nm thick TiO coating were used as conducting AFM tips in this study. We observed the surfaces of superconducting strip lines modified by AFM anodization' process. First, superconducting strip lines with scan size 2 ${\mu}{\textrm}{m}$${\times}$2 ${\mu}{\textrm}{m}$ have been anodized by AFM technology. The surface roughness was increased with the number of AFM scanning, The roughness variation was higher in case of the AFM tip with a positive voltage than with a negative voltage in respect of the strip surface. Second, we have patterned nm-scale oxide lines on ${YBa}-2{Cu}_3{O}_{7-x}$ superconducting microstrip surfaces by AFM conductive cantilever with a negative bias voltage. The ${YBa}-2{Cu}_3{O}_{7-x}$ oxide lines could be patterned by anodization technique. This research showed that the critical characteristics of superconducting thin films were be controlled by AFM anodization process technique. The AFM technique was expected to be used as a promising anodization technique for fabrication of an SFFT with nano-channel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.11a
• /
• pp.683-686
• /
• 2004

In recent years, the supercapacitor and hybrid capacitor have related with substitutional energy source focused of many scientists because of their usage in power sources for electric vehicles, computers and other electric devices. The storage energy of electrical charge is based on electrostatic interactions in the electric double layer at the electrode/electrolyte interface, resulting in high rate capability and long cycle performance compared with batteries based on Faradaic electrode reactions. So we have been considered to carbon nanofibers as the ideal material for supercapacitors due to their high utilization of specific surface area, good conductivity, chemical stability and other advantages. In this work, we aimed to find out that the capacitance have increased because of electrochemical capacitance to provide by carbon nanofibers. Also carbon nanofibers based on chemical method and water treatment have been resulted larger capacitances and also exhibit better electrochemical behaviors about 15% than before of nontreated state. And also optical observations with treated and nontrteated carbon nanofibers discussed by the TEM, SEM, EDX, BET works and specific surface area analyzer. Their results also focused on the surface area of electrode and electrical capacitance was also improved by the effect of surface treatments.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.11a
• /
• pp.136-139
• /
• 2004

The requirement of planarity, such as with-in-wafer nonuniformity, post thickness range, have become increasingly stringent as critical dimensions of devices are decreased and a better control of a planarity become important. The key factors influencing the planarity capability of the CMP process have been well understood through numerous related experiments. These usually include parameters such as process pressures, relative velocities, slurry temperature, polishing pad materials and polishing head structure. Many study have been done about polishing pad and its groove structure because it's considered as one of the key factors which can decide wafer uniformity directly. But, not many study have been done about polisher head structure, especially about polisher head plate design. The purpose of this paper is to know how the plate structure can affect wafer uniformity and how to deteriorate wafer yield. Furthermore, we studied several new designed plate to improve wafer uniformity and also improve wafer yield.