• Journal of IKEEE
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• v.17 no.4
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• pp.570-578
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• 2013

This paper proposed an $8{\times}8$ HEVC inverse core transform architecture reusing multipliers. In HEVC core transform, processing of lower size block is identical with even part of upper size block. So an $8{\times}8$ core transform architecture can process both $8{\times}8$ and $4{\times}4$ core transforms. However, when $8{\times}8$ core transform architecture is exploited, frame processing time doubles in $4{\times}4$ core transform, since $8{\times}8$ and $4{\times}4$ core transforms concurrently process 8 and 4 pixels, respectively. In this paper, a novel inverse core transform architecture is proposed based on multiplier reuse. It runs as an $8{\times}8$ inverse core transformer or two $4{\times}4$ inverse core transformer. Its frame processing time is same in $8{\times}8$ and $4{\times}4$ core transforms, and reduces gate counts by 12%.

• Journal of Engineering Education Research
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• v.10 no.3
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• pp.79-92
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• 2007

To enhance the excellence, effectiveness and economical efficiency in the learning process, we implement a hybrid educational system for engineering experiments where web-based virtual laboratory systems and distance education systems are properly integrated. In the first stage, we designed client/server distributed environment and developed web-based virtual laboratory systems for digital systems and electrical/electronic circuit experiments. The proposed virtual laboratory systems are composed of four important sessions and their management system: concept learning session, virtual experiment session, assessment session. With the aid of the management system every session is organically tied up together to achieve maximum learning efficiency. In the second stage, we have implemented efficient and cost-effective distant laboratory systems for practicing electric/electronic circuits, which can be used to eliminate the lack of reality occurred during virtual laboratory session. The use of simple and user-friendly design allows a large number of people to access our distant laboratory systems easily. Thus, self-guided advanced training is available even if a lot of expensive equipment will not be provided in the on-campus laboratories. The proposed virtual/distant laboratory systems can be used in stand-alone fashion, but to enhance learning efficiency we integrated them and developed a hybrid educational system for engineering experiments. Our hybrid education system provides the learners with interactive learning environment and a new approach for the delivery of engineering experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.24-31
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• 2007

Up to date, a lot of bus protocol and bus architecture are released though most of them are based on the shared bus architecture and inherit the limitation of performance. SNP (SoC Network Protocol), and hence, SNA (SoC Network Architecture) which are high performance on-chip-bus protocol and architecture, respectively, have been proposed to solve the problems of the conventional shared bus. We refine the SNA specification and improve the performance and functionality. The performance of the SNA is improved by supporting simultaneous routing for bus request of multiple masters. The internal routing logic is also improved so that the gate count is decreased. The proposed SNA employs XSNP (extended SNP) that supports almost perfect compatibility with AMBA AHB protocol without performance degradation. The hardware complexity of the improved SNA is not increased much by optimizing the current routing logic. The improved SNA works for IPs with the original SNP at its best performance. In addition, it can also replace the AMBA AHB or interconnect matrix of a system, and it guarantees simultaneous multiple channels. That is, the existing AMBA system can show much improved performance by replacing the AHB or the interconnect matrix with the SNA. Thanks to the small number of interconnection wires, the SNA can be used for the off-chip bus system, too. We verify the performance and function of the proposed SNA and XSNP simulation and emulation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.10
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• pp.131-135
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• 2017

We developed a portable card reader for the visually impaired. In South Korea, there is insufficient development of lifestyle aids for people with disabilities. Living aids for people with disabilities are being developed using information technology, smart phones, Internet of Things(IoT) devices, 3D printers, and so on. Blind people were interviewed, which showed that the card recognition function using a currently developed smart phone app was not able to recognize the screen of the smart phone by the hand of the visually impaired, and it was inconvenient to operate. In recent years, devices that enable the visually impaired to recognize cards have been studied in foreign countries and are emerging prototypes. But what is currently available is expensive and inconvenient. In addition, visually impaired people are most vulnerable to low-income families, which makes it difficult to purchase and use expensive devices. In this study, we developed a card reader that recognizes a card using a Raspberry Pi, which is an open-source hardware that can be applied to IoT. The card reader plays it by voice and vibration, and the visually impaired can use it at a low price.

• Investigative Magnetic Resonance Imaging
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• v.11 no.1
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• pp.10-19
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• 2007

Conventional MRI methods using T1-, T2-, diffusion-, perfusion-weighting, and functional imaging rely on characterizing the physical and functional properties of the tissue. In this review, we introduce an imaging modality based on measured the mechanical properties of soft tissue, namely magnetic resonance elastography (MRE). The use of palpation to identify the stiffness of tissue remains a fundamental diagnostic tool. MRE can quantify the stiffness of the tissue thereby providing a objective means to measure the mechanical properties. To accomplish a successful clinical setting using MRE, hardware and software techniques in the area of transducer, pulse sequence, and imaging processing algorithm need to be developed. Transducer, a mechanical vibrator, is the core of MRE application to make wave propagate invivo. For this reason, considerations of the frame of human body, pressure and friction of the interface, and high magnetic field of a MRI system needs to be taken into account when designing a transducer. Given that the wave propagates through human body effectively, developing an appropriate pulse sequence is another important issue in obtaining an optimal image. In this review paper, we introduce the technical aspects needed for MRE experiments and introduce several applications of this new field.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.9
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• pp.1-8
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• 2010

A digital phase wrapping modulation (DPM) open-loop polar transmitter can be efficiently applied to a wideband orthogonal frequency division multiplexing (OFDM) communication system by converting in-phase and quadrature signals to envelope and phase signals and then employing the signal mapping process. This mapping process is very similar to quantization in a general communication system, and when taking into account the error that appears during mapping process, one can replace the coordinates rotation digital computer (CORDIC) algorithm in the coordinate conversion part with the Taylor series approximation method. In this paper, we investigate the application of the Taylor series approximation to the cartesian to polar coordinate conversion part of a DPM polar transmitter for wideband OFDM systems. The conventional approach relies on the CORDIC algorithm. To achieve efficient application, we perform computer simulation to measure mean square error (MSE) of the both approaches and find the minimum approximation order for the Taylor series approximation compatible to allowable error of the CORDIC algorithm in terms of hardware design. Furthermore, comparing the processing speeds of the both approaches in the implementation with FPGA reveals that the Taylor series approximation with lower order improves the processing speed in the coordinate conversion part.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.2
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• pp.319-326
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• 2020

PRNGs(Pseudorandom number generators) are essential for generating encryption keys for to secure online communication. A bitstream generated by the PRNG must be generated at high speed to encrypt the big data effectively in a symmetric key cryptosystem and should ensure the randomness of the level to pass through the several statistical tests. CA(Cellular Automata) based PRNGs are known to be easy to implement in hardware and to have better randomness than LFSR based PRNGs. In this paper, we design PRNGs based on PMLCA(Programable Maximum Length CA) that can generate effective key sequences in symmetric key cryptosystem. The proposed PRNGs generate bit streams through nonlinear control method. First, we design a PRNG based on an (m,n)-cell PMLCA ℙ with a single complement vector that produces linear sequences with the long period and analyze the period and the generating polynomial of ℙ. Next, we design an (m,n)-cell PC-MLCA based PRNG with two complement vectors that have the same period as ℙ and generate nonlinear sequences, and analyze the location of outputting the nonlinear sequence.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.24-32
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Journal of IKEEE
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• v.19 no.4
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• pp.596-602
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• 2015

In this paper, a unified inverse transformer is designed for HEVC and VP9. The proposed architecture performs all modes of HEVC and VP9 in the unified inverser transformer, such as $4{\times}4{\sim}32{\times}32$ HEVC IDCT, $4{\times}4$ HEVC IDST, $4{\times}4{\sim}32{\times}32$ VP9 IDCT, $4{\times}4{\sim}16{\times}16$ VP9 IADST and $4{\times}4$ IWHT. Same computations are used in HEVC IDCT and VP9 IDCT, except for the scales of the coefficients. Similarly, same computations are used in HEVC $4{\times}4$ IDST and VP9 $4{\times}4$ IADST, except for the scales of the coefficients. Furthermore, HEVC IDCT, VP9 IDCT, and VP9 IADST are the subsets of upper level IDCTs. The proposed architecture reuses multipliers when the computation is identical. Also it shares adders and butterfly structures even when the multiplier coefficients are different. So it reduces the hardware size significantly. Synthesized in 0.18 um technology, the gate count is 456,442 gates. which achieved 22.6% reduction compared to conventional architectures.

• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.2
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• pp.335-343
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• 2024

Real-time target signal processing techniques for FMCW LiDAR are described in this paper. FMCW LiDAR is gaining attention as the next-generation LiDAR for self-driving cars because of its detection robustness even in adverse environmental conditions such as rain, snow and fog etc. in addition to its long range measurement capability. The hardware architecture which is required for high-speed data acquisition, data transfer, and parallel signal processing for frequency-domain signal processing is described in this article. Fourier transformation of the acquired time-domain signal is implemented on FPGA in real time. The paper also details the C-FAR algorithm for ensuring robust target detection from the transformed target spectrum. This paper elaborates on enhancing frequency measurement resolution from the target spectrum and converting them into range and velocity data. The 3D image was generated and displayed using the 2D scanner position and target distance data. Real-time target signal processing and high-resolution image acquisition capability of FMCW LiDAR by using the proposed parallel signal processing algorithms based on FPGA architecture are verified in this paper.