• Proceedings of the Korean Reliability Society Conference
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• 2001.06a
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• pp.273-275
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• 2001

With the continuous advancement in electronics technology, especially the usage of new materials and the introduction of new and immature manufacturing process, stress and time dependent types of physical, chemical and mechanical imperfections are introduced to the electronic hardware. These types of imperfections are called flaws. A reliability stress screening process(RSS) is a process which involves the application of operational and/or environmental stress to electronic hardware on a 100% basis, for the purpose of precipitating inherent, as well as process-induced, flaws while neither destroying nor degrading in a significant way the hardware being stressed.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.2 no.1
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• pp.20-25
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• 2002

This paper presents a genetic programming based evolutionary strategy for on-line adaptive learnable evolvable hardware. Genetic programming can be useful control method for evolvable hardware for its unique tree structured chromosome. However it is difficult to represent tree structured chromosome on hardware, and it is difficult to use crossover operator on hardware. Therefore, genetic programming is not so popular as genetic algorithms in evolvable hardware community in spite of its possible strength. We propose a chromosome representation methods and a hardware implementation method that can be helpful to this situation. Our method uses context switchable identical block structure to implement genetic tree on evolvable hardware. We composed an evolutionary strategy for evolvable hardware by combining proposed method with other's striking research results. Proposed method is applied to the autonomous mobile robots cooperation problem to verify its usefulness.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.5
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• pp.2357-2380
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• 2019

In this paper, we investigate the impact of hardware impairments (HWIs) on the performance of a downlink massive MIMO system. We consider a single-cell system with maximum ratio transmission (MRT) as precoding scheme, and with all the HWIs characteristics such as phase noise, distortion noise, and amplified thermal noise. Based on the system model, we derive closed-form expressions for a typical user data rate under two scenarios: when a common local oscillator (CLO) is used at the base station and when separated oscillators (SLOs) are used. We also derive closed-form expressions for the downlink transmit power required for some desired per-user data rate under each scenario. Compared to the conventional system with ideal transceiver hardware, our results show that impairments of hardware make a finite upper limit on the user's downlink channel capacity; and as the number of base station antennas grows large, it is only the hardware impairments at the users that mainly limit the capacity. Our results also show that SLOs configuration provides higher data rate than CLO at the price of higher power consumption. An approach to minimize the effect of the hardware impairments on the system performance is also proposed in the paper. In our approach, we show that by reducing the cell size, the effect of accumulated phase noise during channel estimation time is minimized and hence the user capacity is increased, and the downlink transmit power is decreased.

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.8
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• pp.746-753
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• 2001

In this paper, we review the basic concept of Evolvable Hardware first. And we examine genetic algorithm processor and hardware reconfiguration method and implementation. By considering complexity and performance of hardware at the same time, we design genetic algorithm processor using modularization and parallel processing method. And we design frame that has connection structure and logic block on FPGA, and embody reconfigurable hardware that do so that this frame may be reconstructed by RAM. Also we implemented ECANS that information processing system such as living creatures'brain using this hardware reconfiguration method. And we apply ECANS which is implemented using the concept of Evolvable Hardware to time-series prediction problem in order to verify the effectiveness.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.3 no.1
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• pp.23-26
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• 2003

This paper proposes a new artificial immune approach to hardware test. A novel algorithm of generating tolerance conditions is suggested based on the principle of the antibody diversity. Tolerance conditions in artificial immune system correspond to the antibody in biological immune system. The suggested method is applied to the on-line monitoring of a typical FSM (a decade counter) and its effectiveness is demonstrated by the computer simulation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.9
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• pp.4295-4316
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• 2018

In this paper, the performance of non-orthogonal multiple access (NOMA) dual-hop (DH) amplify-and-forward (AF) relaying networks is investigated, where Nakagami-m fading channel is considered. In order to cover more details, in our analysis, the transceiver hardware impairments at source, relay and destination nodes are comprehensively considered. To characterize the effects of hardware impairments brought in NOMA DH AF relaying networks, the analytical closed-form expressions for the exact outage probability and approximate ergodic sum rate are derived. In addition, the asymptotic analysis of the outage probability and ergodic sum rate at high signal-to-noise ratio (SNR) regime are carried out in order to further reveal the insights of the parameters for hardware impairments on the network performance. Simulation results indicate the performance of asymptotic ergodic sum rate are limited by levels of distortion noise.

• Transactions of the Korean Society of Automotive Engineers
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• v.7 no.9
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• pp.105-111
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• 1999

The paper presents development of a Hardware-In-the-Loop simulation (HILS) system for the purpose of testing performance, stability, and reliability of an electronic power steering system(EPS). In order to realistically test an EPS by the proposed HILS apparatus, a simulated uniaxial dynamic rack force is applied physically to the EPS hardware by a pnumatic actuator. An EPS hardware is composed of steering wheel &column, a rack & pinion mechanism, andas motor-driven power steering system. A command signal for a pneumatic rack-force actuator is generated from the vehicle handling lumped parameter dynamic model 9software) that is simulated in real time by using a very fast digital signal processor. The inputs to the real-time vehicle dynamic simulation model are a constant vehicle forward speed and from wheel steering angles driven through a steering system by a driver. The output from a real-time simulation model is an electric signal that is proportional to the uniaxial rack force. The vehicle handling lumped parameter dynamic model is validated by a fully nonlinear constrained multibody vehicle dynamic model. The HILS system simulation results sow that the proposed HILS system may be used to realistically test the performance stability , and reliability of an electronic power steering system is a repeated way.

• Advances in Automotive Engineering
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• v.1 no.1
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• pp.123-141
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• 2018

Hardware-in-the-loop (HiL) simulation is a very powerful tool to design, test and verify automotive control systems. However, well-validated and high degree of freedom vehicle models have to be utilized in these simulations in order to obtain realistic results. In this paper, a vehicle dynamics model developed in the Carsim Real Time program environment and its validation has been performed using experimental results. The developed Carsim real time model has been employed in the Tofas R&D hardware-in-the-loop simulator. Experimental and hardware-in-the-loop simulation results have been compared for the standard FMVSS No. 126 test and the results have been found to be in good agreement with each other. Two electronic stability control (ESC) algorithms, named the Basic ESC and the Integrated ESC, taken from the earlier work of the authors have been tested and evaluated in the hardware-in-the-loop simulator. Different evaluation methods have been formulated and used to compare these ESC algorithms. As a result, the Integrated ESC system has been shown superior performance as compared to the Basic ESC algorithm.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.192-197
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• 2017

In this paper, image filter optimization method based on common sub-expression elimination is proposed for low-power image feature extraction hardware design. Low power and high performance object recognition hardware is essential for industrial robot which is used for factory automation. However, low area Gaussian gradient filter hardware design is required for object recognition hardware. For the hardware complexity reduction, we adopt the symmetric characteristic of the filter coefficients using the transposed form FIR filter hardware architecture. The proposed hardware architecture can be implemented without degradation of the edge detection data quality since the proposed hardware is implemented with original Gaussian gradient filtering algorithm. The expremental result shows the 50% of multiplier savings compared with previous work.

• ETRI Journal
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• v.31 no.3
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• pp.339-341
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• 2009

Built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. In this letter, a new BIRA method for both high repair efficiency and small hardware overhead is presented. The proposed method performs redundancy analysis operations using the spare mapping registers with a covered fault list. Experimental results demonstrate the superiority of the proposed method compared to previous works.