• Title/Summary/Keyword: Electrode geometry

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Electrical Characteristic of IGZO Oxide TFTs with 3 Layer Gate Insulator

  • Lim, Sang Chul;Koo, Jae Bon;Park, Chan Woo;Jung, Soon-Won;Na, Bock Soon;Lee, Sang Seok;Cho, Kyoung Ik;Chu, Hye Yong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.344-344
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    • 2014
  • Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

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Two-dimensional Simulation Study on Optimization of Gate Field Plate Structure for High Breakdown Voltage AlGaN/GaN-on-Si High Electron Mobility Transistors (고내압 전력 스위칭용 AlGaN/GaN-on-Si HEMT의 게이트 전계판 구조 최적화에 대한 이차원 시뮬레이션 연구)

  • Lee, Ho-Jung;Cho, Chun-Hyung;Cha, Ho-Young
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.12
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    • pp.8-14
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    • 2011
  • The optimal geometry of the gate field plate in AlGaN/GaN-on-Si HEMT has been proposed using two-dimensional device simulation to achieve a high breakdown voltage for a given gate-to-drain distance. It was found that the breakdown voltage was drastically enhanced due to the reduced electric field at the gate corner when a gate field plate was employed. The electric field distribution at the gate corner and the field plate edge was investigated as functions of field plate length and insulator thickness. According to the simulation results, the electric field at the gate corner can be successfully reduced even with the field plate length of 1 ${\mu}m$. On the other hand, when the field plate length is too long, the distance between field plate and drain electrode is reduced below a critical level, which eventually lowers the breakdown voltage. The highest breakdown voltage was achieved with the field plate length of 1 ${\mu}m$. According to the simulation results varying the $SiN_x$ film thickness for the fixed field plate length of 1 ${\mu}m$, the optimum thickness range of the $SiN_x$ film was 200 - 300 nm where the electric field strength at the field plate edge counterbalances that of the gate corner.

CdZnTe Detector for Computed Tomography based on Weighting Potential (가중 퍼텐셜에 기초한 CT용 CdZnTe 소자 설계)

  • Lim, Hyunjong;Park, Chansun;Kim, Jungsu;Kim, Jungmin;Choi, Jonghak;Kim, KiHyun
    • Journal of radiological science and technology
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    • v.39 no.1
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    • pp.35-42
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    • 2016
  • Room-temperature operating CdZnTe(CZT) material is an innovative radiation detector which could reduce the patient dose to one-tenth level of conventional CT (Computed Tomography) and mammography system. The pixel and pixel pitch in the imaging device determine the conversion efficiency of incident X-or gamma-ray and the cross-talk of signal, that is, image quality of detector system. The weighting potential is the virtual potential determined by the position and geometry of electrode. The weighting potential obtained by computer-based simulation in solving Poisson equation with proper boundaries condition. The pixel was optimized by considering the CIE (charge induced efficiency) and the signal cross-talk in CT detector system. The pixel pitch was 1-mm and the detector thickness was 2-mm in the simulation. The optimized pixel size and inter-pixel distance for maximizing the CIE and minimizing the signal cross-talk is about $750{\mu}m$ and $125{\mu}m$, respectively.

Dead Layer Thickness and Geometry Optimization of HPGe Detector Based on Monte Carlo Simulation

  • Suah Yu;Na Hye Kwon;Young Jae Jang;Byungchae Lee;Jihyun Yu;Dong-Wook Kim;Gyu-Seok Cho;Kum-Bae Kim;Geun Beom Kim;Cheol Ha Baek;Sang Hyoun Choi
    • Progress in Medical Physics
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    • v.33 no.4
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    • pp.129-135
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    • 2022
  • Purpose: A full-energy-peak (FEP) efficiency correction is required through a Monte Carlo simulation for accurate radioactivity measurement, considering the geometrical characteristics of the detector and the sample. However, a relative deviation (RD) occurs between the measurement and calculation efficiencies when modeling using the data provided by the manufacturers due to the randomly generated dead layer. This study aims to optimize the structure of the detector by determining the dead layer thickness based on Monte Carlo simulation. Methods: The high-purity germanium (HPGe) detector used in this study was a coaxial p-type GC2518 model, and a certified reference material (CRM) was used to measure the FEP efficiency. Using the MC N-Particle Transport Code (MCNP) code, the FEP efficiency was calculated by increasing the thickness of the outer and inner dead layer in proportion to the thickness of the electrode. Results: As the thickness of the outer and inner dead layer increased by 0.1 mm and 0.1 ㎛, the efficiency difference decreased by 2.43% on average up to 1.0 mm and 1.0 ㎛ and increased by 1.86% thereafter. Therefore, the structure of the detector was optimized by determining 1.0 mm and 1.0 ㎛ as thickness of the dead layer. Conclusions: The effect of the dead layer on the FEP efficiency was evaluated, and an excellent agreement between the measured and calculated efficiencies was confirmed with RDs of less than 4%. It suggests that the optimized HPGe detector can be used to measure the accurate radioactivity using in dismantling and disposing medical linear accelerators.