• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.133-133
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• 2008

Recently, as the down-scailing of field-effect transistor devices continues, Schottky-barrier field-effect transistors (SB-FETs) have attracted much attention as an alternative to conventional MOSFETs. SB-FETs have advantages over conventional devices, such as low parasitic source/drain resistance due to their metallic characteristics, low temperature processing for source/drain formation and physical scalability to the sub-10nm regime. The good scalability of SB-FETs is due to their metallic characteristics of source/drain, which leads to the low resistance and the atomically abrupt junctions at metal (silicide)-silicon interface. Nevertheless, some reports show that SB-FETs suffer from short channel effect (SCE) that would cause severe problems in the sub 20nm regime.[Ouyang et al. IEEE Trans. Electron Devices 53, 8, 1732 (2007)] Because source/drain barriers induce a depletion region, it is possible that the barriers are overlapped in short channel SB-FETs. In order to analyze the SCE of SB-FETs, we carried out systematic studies on the Schottky barrier overlapping in short channel SB-FETs using a SILVACO ATLAS numerical simulator. We have investigated the variation of surface channel band profiles depending on the doping, barrier height and the effective channel length using 2D simulation. Because the source/drain depletion regions start to be overlapped each other in the condition of the $L_{ch}$~80nm with $N_D{\sim}1\times10^{18}cm^{-3}$ and $\phi_{Bn}$ $\approx$ 0.6eV, the band profile varies as the decrease of effective channel length $L_{ch}$. With the $L_{ch}$~80nm as a starting point, the built-in potential of source/drain schottky contacts gradually decreases as the decrease of $L_{ch}$, then the conduction and valence band edges are consequently flattened at $L_{ch}$~5nm. These results may allow us to understand the performance related interdependent parameters in nanoscale SB-FETs such as channel length, the barrier height and channel doping.

• Asian-Australasian Journal of Animal Sciences
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• v.11 no.5
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• pp.597-607
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• 1998

Processing is generally employed to alter the physical and chemical properties of feeds used in pig diets, using hammer/roller mills, pellet mills and extruders/expanders. The reported optimum particle sizes of corn are approximately $500{\mu}m$, $500-700{\mu}m$, $400-600{\mu}m$, for nursery, growing-finishing, and breeder pigs respectively. Optimum particle size of grains are affected by diet complexity. There was a trend towards reducing particle size in order to increase ADG in pigs fed a simple diet, though such was not the case for pigs fed a complex diet. Uniformity of particle size also affects the nutritional values of swine feeds. Uniform particle sizes would consistently give greater nutrient digestibilities. In terms of pellet quality, it is reported that a higher incidence of fmes in pelleted feeds has a direct correlation with poorer feed conversion ratio in pigs. Particle and pellet sizes are also very important for pelleting in terms of grinding, digestibility, stomach ulceration and pellet durability. A particle size of $600{\mu}m$, or slightly less, seemed optimal for com in fmishing pigs, and the 5/32 in. diameter pellets supported the best efficiencies of gain during nursery and finishing phases. Extruder and/or expander processes would allow the feed industry an increased flexibility to utilize a wider spectrum of feed ingredients, and improve pellet quality of finished feeds. It would appear that extruded or expanded diets containing highly digestible ingredients have little effect on the growth performance of pigs, and the feeding values of the feeds over pelleted diets were not improved as pigs grew. The extruder or expander is much more effective than a pelletizer in salmonella control. Gastric ulcerations and/or keratinizations were consistently reported in pigs fed mash and processed diets containing finely ground grains, whereas carcass quality was not affected by diet processing methods such as pelleting, extruding or expanding. In corn- or sorghum-based diets, the electrical energy consumption is 4-5 times higher in the expanding than in the pelleting process. But the expander's processing cost was half of that shown by an extruder. Finally, the decision of which feed processing technology to adopt would depend on the processing cost, and any potential improvement in growth performance and digestibilities of nutrients should offset the increased operating and capital costs related to the extruder/expander technology over mash or pelleting processes in pigs.

• Korean Journal of Materials Research
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• v.30 no.10
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• pp.566-572
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• 2020

In the recent years, thin film solar cells (TFSCs) have emerged as a viable replacement for crystalline silicon solar cells and offer a variety of choices, particularly in terms of synthesis processes and substrates (rigid or flexible, metal or insulator). Among the thin-film absorber materials, SnS has great potential for the manufacturing of low-cost TFSCs due to its suitable optical and electrical properties, non-toxic nature, and earth abundancy. However, the efficiency of SnS-based solar cells is found to be in the range of 1 ~ 4 % and remains far below those of CdTe-, CIGS-, and CZTSSe-based TFSCs. Aside from the improvement in the physical properties of absorber layer, enormous efforts have been focused on the development of suitable buffer layer for SnS-based solar cells. Herein, we investigate the device performance of SnS-based TFSCs by introducing double buffer layers, in which CdS is applied as first buffer layer and ZnMgO films is employed as second buffer layer. The effect of the composition ratio (Mg/(Mg+Zn)) of RF sputtered ZnMgO films on the device performance is studied. The structural and optical properties of ZnMgO films with various Mg/(Mg+Zn) ratios are also analyzed systemically. The fabricated SnS-based TFSCs with device structure of SLG/Mo/SnS/CdS/ZnMgO/AZO/Al exhibit a highest cell efficiency of 1.84 % along with open-circuit voltage of 0.302 V, short-circuit current density of 13.55 mA cm^-2, and fill factor of 0.45 with an optimum Mg/(Mg + Zn) ratio of 0.02.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.701-713
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• 2009

This paper studies a method for reducing performance degradation due to losing sub-carrier orthogonality caused by power transient between physical channels in LTE uplink transmission. The pattern of inter-carrier interference(ICI) caused by power transient is different from what has been studied for doppler shift, in that its pattern occurs at front and rear sides of channels in each period of power transient. The reason of ICI's occurrence results from power difference between channels, power transient duration, multi-path channel delay spread, and numbers of sub-carrier. New criterion is proposed to find out number of taps of multi-tap equalizer enough to improve the ICI. The scheme is to determine the number of taps of multi-tap equalizer when a normalized interference or a normalized ICI is greater than a normalized noise. Simulation results show that the number of taps is flexibly adjusted according to SNR(Signal to Noise Ratio) of a received signal to improve Bit Error Rate(BER), while the complexity of the proposed scheme is reduced down to 88 percentage of the classical method.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.19-25
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• 2011

The size reduction of the semiconductor chip and the improvement of the electrical performance have been enabled through the introduction of the Cu/Low-K process in modern electronic industries. However, Cu/Low-K has a disadvantage of the physical properties that is weaker than materials used for existing semiconductor manufacture process. It causes many problems in chip manufacturing and package processes. Especially, the delamination between the Cu layer and the low-K dielectric layer is a main defect after the temperature cycles. Since the Cu/Low-K layer is located on the top of the pad of the flip chip, the stress on the flip chip affects the Cu/Low-K layer directly. Therefore, it is needed to improve the underfill process or materials. Especially, it becomes very important to select the underfill to decrease the stress at the flip-chip and to protect the solder bump. We have solved the delamination problem in a 90 nm Cu/Low-K flip-chip package after the temperature cycle by selecting an appropriate underfill.

• Journal of the Korean Vacuum Society
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• v.17 no.6
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• pp.518-522
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• 2008

The miniaturization of device size and multilevel interlayers have been developed by ULSI circuit devices. These submicron processes cause serious problems in conventional metallization due to the solubility of silicon and metal at the interface, such as an increasing contact resistance in the contact hole and interdiffusion between metal and silicon. Therefore it is necessary to implement a barrier layer between Si and metal. Thus, the size of multilevel interconnection of ULSI devices is critical metallization schemes, and it is necessary reduce the RC time delay for device speed performance. So it is tendency to study the Cu metallization for interconnect of semiconductor processes. However, at the submicron process the interaction between Si and Cu is so strong and detrimental to the electrical performance of Si even at temperatures below $200^{\circ}C$. Thus, we suggest the tungsten-carbon-nitrogen (W-C-N) thin film for Cu diffusion barrier characterized by nano scale indentation system. Nano-indentation system was proposed as an in-situ and nanometer-order local stress analysis technique.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.3 s.36
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• pp.197-205
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• 2005

Development of the packaging is one of the critical issues for commercialization of the RF-MEMS devices. RF MEMS package should be designed to have small size, hermetic protection, good RF performance and high reliability. In addition, packaging should be conducted at sufficiently low temperature. In this paper, a low temperature hermetic wafer level packaging scheme for the RF-MEMS devices is presented. For hermetic sealing, Au-Sn eutectic bonding technology at the temperature below $300{\times}C$ is used. Au-Sn multilayer metallization with a square loop of $70{\mu}m$ in width is performed. The electrical feed-through is achieved by the vertical through-hole via filled with electroplated Cu. The size of the MEMS Package is $1mm\times1mm\times700{\mu}m$. By applying $O_2$ plasma ashing and fabrication process optimization, we can achieve the void-free structure within the bonding interface as well as via hole. The shear strength and hermeticity of the package satisfy the requirements of MIL-STD-883F. Any organic gases or contamination are not observed inside the package. The total insertion loss for the packaging is 0.075 dB at 2 GHz. Furthermore, the robustness of the package is demonstrated by observing no performance degradation and physical damage of the package after several reliability tests.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.100-101
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• 2012

The plasma damage free and room temperature processedthin film deposition technology is essential for realization of various next generation organic microelectronic devices such as flexible AMOLED display, flexible OLED lighting, and organic photovoltaic cells because characteristics of fragile organic materials in the plasma process and low glass transition temperatures (Tg) of polymer substrate. In case of directly deposition of metal oxide thin films (including transparent conductive oxide (TCO) and amorphous oxide semiconductor (AOS)) on the organic layers, plasma damages against to the organic materials is fatal. This damage is believed to be originated mainly from high energy energetic particles during the sputtering process such as negative oxygen ions, reflected neutrals by reflection of plasma background gas at the target surface, sputtered atoms, bulk plasma ions, and secondary electrons. To solve this problem, we developed the NBAS (Neutral Beam Assisted Sputtering) process as a plasma damage free and room temperature processed sputtering technology. As a result, electro-optical properties of NBAS processed ITO thin film showed resistivity of $4.0{\times}10^{-4}{\Omega}{\cdot}m$ and high transmittance (>90% at 550 nm) with nano- crystalline structure at room temperature process. Furthermore, in the experiment result of directly deposition of TCO top anode on the inverted structure OLED cell, it is verified that NBAS TCO deposition process does not damages to the underlying organic layers. In case of deposition of transparent conductive oxide (TCO) thin film on the plastic polymer substrate, the room temperature processed sputtering coating of high quality TCO thin film is required. During the sputtering process with higher density plasma, the energetic particles contribute self supplying of activation & crystallization energy without any additional heating and post-annealing and forminga high quality TCO thin film. However, negative oxygen ions which generated from sputteringtarget surface by electron attachment are accelerated to high energy by induced cathode self-bias. Thus the high energy negative oxygen ions can lead to critical physical bombardment damages to forming oxide thin film and this effect does not recover in room temperature process without post thermal annealing. To salve the inherent limitation of plasma sputtering, we have been developed the Magnetic Field Shielded Sputtering (MFSS) process as the high quality oxide thin film deposition process at room temperature. The MFSS process is effectively eliminate or suppress the negative oxygen ions bombardment damage by the plasma limiter which composed permanent magnet array. As a result, electro-optical properties of MFSS processed ITO thin film (resistivity $3.9{\times}10^{-4}{\Omega}{\cdot}cm$, transmittance 95% at 550 nm) have approachedthose of a high temperature DC magnetron sputtering (DMS) ITO thin film were. Also, AOS (a-IGZO) TFTs fabricated by MFSS process without higher temperature post annealing showed very comparable electrical performance with those by DMS process with $400^{\circ}C$ post annealing. They are important to note that the bombardment of a negative oxygen ion which is accelerated by dc self-bias during rf sputtering could degrade the electrical performance of ITO electrodes and a-IGZO TFTs. Finally, we found that reduction of damage from the high energy negative oxygen ions bombardment drives improvement of crystalline structure in the ITO thin film and suppression of the sub-gab states in a-IGZO semiconductor thin film. For realization of organic flexible electronic devices based on plastic substrates, gas barrier coatings are required to prevent the permeation of water and oxygen because organic materials are highly susceptible to water and oxygen. In particular, high efficiency flexible AMOLEDs needs an extremely low water vapor transition rate (WVTR) of $1{\times}10^{-6}gm^{-2}day^{-1}$. The key factor in high quality inorganic gas barrier formation for achieving the very low WVTR required (under ${\sim}10^{-6}gm^{-2}day^{-1}$) is the suppression of nano-sized defect sites and gas diffusion pathways among the grain boundaries. For formation of high quality single inorganic gas barrier layer, we developed high density nano-structured Al2O3 single gas barrier layer usinga NBAS process. The NBAS process can continuously change crystalline structures from an amorphous phase to a nano- crystalline phase with various grain sizes in a single inorganic thin film. As a result, the water vapor transmission rates (WVTR) of the NBAS processed $Al_2O_3$ gas barrier film have improved order of magnitude compared with that of conventional $Al_2O_3$ layers made by the RF magnetron sputteringprocess under the same sputtering conditions; the WVTR of the NBAS processed $Al_2O_3$ gas barrier film was about $5{\times}10^{-6}g/m^2/day$ by just single layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.642-642
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• 2013

Graphene, two dimensional single layer of carbon atoms, has tremendous attention due to its superior property such as high electron mobility, high thermal conductivity and optical transparency. Especially, chemical vapor deposition (CVD) grown graphene has been used as a promising material for high quality and large-scale graphene film. Unfortunately, although CVD-grown graphene has strong advantages, application of the CVD-grown graphene is limited due to ineffective transfer process that delivers the graphene onto a desired substrate by using polymer support layer such as PMMA(polymethyl methacrylate). The transferred CVD-grown graphene has serious drawback due to remaining polymeric residues generated during transfer process, which induces the poor physical and electrical characteristics by a p-doping effect and impurity scattering. To solve such issue incurred during polymer transfer process of CVD-grown graphene, various approaches including thermal annealing, chemical cleaning, mechanical cleaning have been tried but were not successful in getting rid of polymeric residues. On the other hand, lithographical patterning of graphene is an essential step in any form of microelectronic processing and most of conventional lithographic techniques employ photoresist for the definition of graphene patterns on substrates. But, application of photoresist is undesirable because of the presence of residual polymers that contaminate the graphene surface consistent with the effects generated during transfer process. Therefore, in order to fully utilize the excellent properties of CVD-grown graphene, new approach of transfer and patterning techniques which can avoid polymeric residue problem needs to be developed. In this work, we carried out transfer and patterning process simultaneously with no polymeric residue by using a metal etch mask. The patterned thin gold layer was deposited on CVD-grown graphene instead of photoresists in order to make much cleaner and smoother surface and then transferred onto a desired substrate with PMMA, which does not directly contact with graphene surface. We compare the surface properties and patterning morphology of graphene by scanning electron microscopy (SEM), atomic force microscopy(AFM) and Raman spectroscopy. Comparison with the effect of residual polymer and metal on performance of graphene FET will be discussed.

• Journal of IKEEE
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• v.23 no.1
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• pp.80-90
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• 2019

Even though Non-Volatile Memory (NVM) is used for data storage, a page table should be built to access data in it. And this observation leads us to the Persistent Page Table (PPT) scheme that keeps the page table in NVM persistently. By the way, processors have different page table structures and really operational page table cannot be built without virtual and physical addresses of NVM. However, those addresses are determined dynamically when NVM storage is attached to the system. Thus, the PPT should have system-independent and also address-independent structure and really working system-dependent page table should be built from the PPT. Moreover, entries of PPT should be updated atomically and, in this paper, we describe the design of PPT that meets those requirements. And we investigate how file systems can decrease the journaling overhead with the swap operation, which is a new operation created by the PPT. We modified the Ext4 file system in Linux and experiments conducted with Filebench workloads show that the swap operation enhances file system performance up to 60%.