• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.149-155
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• 2006

In this study, the design of low voltage DC-DC converter with low triggering ESD (Electro-Static Discharge) protection circuit was investigated. The purpose of this paper is design optimization for low voltage(2.5V to 5.5V input range) DC-DC converter using CMOS switch. In CMOS switch environment, a dominant loss component is not switching loss but conduction loss at 1.2MHz switching frequency. In this study a constant frequency PWM converter with synchronous rectifier is used. And zener Triggered SCR device to protect the ESD phenomenon was designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 8V.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.2
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• pp.150-154
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• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.54-60
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• 2007

In this study novel ESD protection device, namely, N/P-type Low Voltage Triggered SCR, has been proposed, for high speed I/O interface. Proposed device could lower high trigger voltage($\sim$20V) of conventional SCR and reduce latch-up phenomenon of protection device during the normal condition. In this Study, the proposed NPLVTSCR has been simulated using TMA MEDICI device simulator for electrical characteristic. Also the proposed device's test pattern was fabricated using 90nm TSMC's CMOS process and was measured electrical characteristic and robustness. In the result, NPLVTSCR has 3.2V $\sim$ 7.5V trigger voltage and 2.3V $\sim$ 3.2V holding voltage by changing PMOS gate length and it has about 2kV, 7.5A HBM ESD robustness(IEC61000-4-2).

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.2
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• pp.319-324
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• 2014

The wafer carrier is made of PP, PC, PE resin which have excellent heat and chemical resistance and electrical properties. However, particle generation has become a problem due to static electricity generated in the carrier. Some conductive material such as carbon black (CB) and carbon fiber (CF) are added for the purpose of anti-static, however, additional for motility and particle contamination problems due to high carbon content occurs. In this paper, the electrical characteristics and workability are observed and compared by adding low Carbon Nono Tube(CNT) to each PP, PC and PE resin to solve the problem.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.10
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• pp.979-986
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• 2013

In this paper, a TVS diode which is commonly used as a ESD protector in wireless communication devices could cause antenna wireless sensitivity to decrease has been analyzed. When a smartphone doesn't have enough space to place many components, there would be its speaker near antenna area. In order to protect ESD coming through the speaker there also could be a TVS within antenna GND area. Digital audio signal which was sent to speaker and CDMA RF communication signal coupled from antenna was mixed by TVS. And this leakage current running through TVS resulted in decrease of antenna wireless sensitivity. The results of various experiments can be explained using circuit simulation. Following works will give us some insights that can reduce unwanted summation of digital and RF signal due to nonlinearity of ESD protectors.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1673-1681
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• 2015

A low dropout (LDO) regulator with a wide-bandwidth is proposed in this paper. The regulator features a Human Body Model (HBM) 8kV-class high robustness ElectroStatic Discharge (ESD) protection circuit, and two error amplifiers (one with low gain and wide bandwidth, and the other with high gain and narrow bandwidth). The dual error amplifiers are located within the feedback loop of the LDO regulator, and they selectively amplify the signal according to its ripples. The proposed LDO regulator is more efficient in its regulation process because of its selective amplification according to frequency and bandwidth. Furthermore, the proposed regulator has the same gain as a conventional LDO at 62 dB with a 130 kHz-wide bandwidth, which is approximately 3.5 times that of a conventional LDO. The proposed device presents a fast response with improved load and line regulation characteristics. In addition, to prevent an increase in the area of the circuit, a body-driven fabrication technique was used for the error amplifier and the pass transistor. The proposed LDO regulator has an input voltage range of 2.5 V to 4.5 V, and it provides a load current of 100 mA in an output voltage range of 1.2 V to 4.1 V. In addition, to prevent damage in the Integrated Circuit (IC) as a result of static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class (Chip level) ESD protection circuit of a P-substrate-Triggered Silicon Controlled Rectifier (PTSCR) type with high robustness characteristics.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1593-1594
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• 2006

본 논문에서는 모바일 컨버젼스 단말기를 위한 Tunable Image Rejection Filter를 구현 하였다. 이 필터는 TSMC 0.25um 공정을 이용해 시뮬레이션 되었다. 또한 정전기로 인한 소자의 파괴를 방지하기 위해 ESD 패드(Electro Static Discharge Pad)를 추가하였다. 영상 주파수 저지 특성은 WCDMA(2.1GHz), WiBro(2.3GHz), WLAN(2.45) 대역에서 모두 28dB 이상이고, 이때 바이어스 전압은 각각 0.5V, 0.95v, 1.8V의 전압을 가지게 되었다. 삽입 손실은 세 대역에서 모두 2dB 이하이다.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.43-47
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• 2004

We have been using Moisture Barrier Bags for dry packing of semiconductor packages to prevent moisture from absorbing during shipping. Moisture barrier bag material is required to be waterproof, vapor proof and offer superior ESD (Electro-static discharge) and EMI shielding. Also, the bag should be formed easily to the shape of products for vacuum packing while providing excellent puncture resistance and offer very low gas ＆ moisture permeation. There are some problems like pinholes and punctured bags after sealing and before the surface mount process. This failure may easily result in package pop corn crack during board mounting. The bags should be developed to meet the requirements of excellent electrical and physical properties by means of optimization of their raw material composition and their thickness. This study investigates the performance of moisture barrier bags by characterization of their mechanical endurance, tensile strength and through thermal analysis. By this study, we arrived at a robust material composition (polyester/Aluminate) for better packing.