• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.2126-2130
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• 2003

In the integrated systems, that is integrated digital TV(DTV) internet and home automation, like home server, is needed integration of digital TV video signal and computer graphic signal. The graphic signal is operating at the high speed and has time-divide-stream. So the re-request of data is not easy at the time of error detection. therefore EDAC algorithm is efficient. In this paper, we show a scheme, that is integration of graphic and dtv format signal for DTV monitor display. This paper also presents the efficiency error detection auto correction(EDAC) for conversion of graphics signal to DTV video signal. A presented EDAC algorithms use the modified hamming code for enhancing video quality and reliability. A EDAC algorithm of this paper can detect single error, double error, triple error and more error for preventing from incorrect correction. And it is not necessary an additional memory. In this paper The comparison between digital TV video signal and graphic signal, a EDAC algorithm and a design of conversion graphic signal to DTV signal with EDAC function in DTV system is described.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.106-109
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• 2002

In the integrated systems, that is integrated digital TV(DTV) internet and home automation, like home server, is needed integration of digital TV video signal and computer graphic signal. The graphic signal is operating at the high speed and has time-divide-stream. So the re-request of data is not easy at the time of error detection. therefore EDAC algorithm is efficient. This paper presents the efficiency error detection auto correction(EDAC) for conversion of graphics signal to DTV video signal. A presented EDAC algorithms use the modified Hamming code for enhancing video quality and reliability. A EDAC algorithm of this paper can detect single error, double error, triple error and more error for preventing from incorrect correction. And it is not necessary an additional memory. In this paper The comparison between digital TV video signal and graphic signal, a EBAC algorithm and a design of conversion graphic signal to DTV signal with EDAC function is described.

• 전기학회논문지
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• 제59권2호
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• pp.417-422
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• 2010

When memory devices are exposed to space environments, they suffer various effects such as SEU(Single Event Upset). Memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, several error detection and correction codes - RS(10,8) code, (7,4) Hamming code and (16,8) code - are analyzed and compared with each other. Each code is implemented using VHDL and its performances(encoding/decoding speed, required memory size) are compared. Also the failure probability equation of each EDAC code is derived, and the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. Finally, the EDAC algorithm for STSAT-3 is determined based on the comparison results.

• 의료ㆍ복지 건축 : 한국의료복지건축학회 논문집
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• 제25권1호
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• pp.61-66
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• 2019

• Journal of Astronomy and Space Sciences
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• 제22권4호
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• pp.537-558
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• 2005

본 논문에서는 HAUSAT-2위성이 운용될 케도의 우주 방사능 환경 및 총 피폭효과(Total Ionizing Dose), 단일사건 효과(Single Event Effects) 등에 대해 분석하였다. 총 피폭효과에 영향을 미치는 우주 방사능은 포획된 양성자, 전자, 태양 양성자 및 우주선이다. 총 피폭효과는 선량 심도선 분석을 통해 해석을 수행하였으며, DMBP(Design Margin Breakpoint) 방법과 3-D 구분구적법을 이용하여 HAVSAT-2의 부품의 총 피폭량에 대한 내성을 검증하였다. 단일사건 효과에 대하여 위성체 외부와 내부 방사능 환경으로 양성자와 중이온에 대하여 선형에너지 전달량(LET) 스펙트럼을 분석하였으며, HAUSAT-2의 전자소자로 사용예정인 MPC860T2B 마이크로프로세서와 메모리 K6X8008T2B에 대한 SEU(Single Event Upset) 및 SEL(Single Event Latch-up) 발생률을 추정하였다. 분석 결과 SEU는 운용 중에 수차례 발생하며 SEL 발생은 임무기간동안 일어나지 않을 것으로 추정되었다. HAUSAT-2는 소프트웨어 해밍코드 EDAC을 이용하여 SEU 발생에 대처할 수 있는 시스템 레벨의 설계를 반영하였다. 이 연구에서 수행된 방사능 해석은 ESA의 SPENVIS소프트웨어를 이용하였다.

• Tuberculosis and Respiratory Diseases
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• 제78권4호
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• pp.455-458
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• 2015

Excessive dynamic airway collapse (EDAC) is a disease entity of excessive reduction of the central airway diameter during exhalation, without cartilage collapse. An 80-year-old female presented with generalized edema and dyspnea at our hospital. The patient was in a state of acute decompensated heart failure due to pneumonia with respiratory failure. We accordingly managed the patient with renal replacement therapy, mechanical ventilation and antibiotics. Bronchoscopy confirmed the diagnosis of EDAC. We scheduled extubation after the improvement of pneumonia and heart condition. However, extubation failure occurred due to hypercapnic respiratory failure with poor expectoration. Her EDAC was improved in response to high flow nasal oxygen therapy (HFNOT). Subsequently, the patient was stabilized and transferred to the general ward. HFNOT, which generates physiologic positive end expiratory pressure (PEEP) effects, could be an alternative and effective management of EDAC. Further research and clinical trials are needed to demonstrate the therapeutic effect of HFNOT on EDAC.

• 제어로봇시스템학회논문지
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• 제6권2호
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• pp.228-233
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• 2000

It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.

• 항공우주기술
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• 제2권1호
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• pp.73-79
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• 2003

대부분의 위성 설계에서 우주 방사선에 의한 메모리 데이터 보호를 위해 오류정정회로를 내장하며, 동시에 오류의 누적을 방지하기 위해 주기적으로 메모리 내용을 읽는 알고리즘을 적용하고 있다. 소프트웨어에 의한 읽기 알고리즘을 적용하는 KOMPSAT 2호기의 경우 메모리 소자에 대한 방사능 영향 시험을 수행하지 않아 1호기에 비해 다소 큰 오류 가능성이 예측되었다. 소프트웨어 알고리즘 변경으로 읽기 작업을 하도록 결정하였으나 하드웨어에 의해 더 빠른 속도로 오류를 정정하도록 하는 방법도 연구되었다. 본 논문은 이러한 연구 결과로서, 최소 1.88분 정도의 주기로 1 Gbits의 메모리 영역을 읽음으로서 하드웨어만으로 메모리 내용을 보존할 수 있는 방법에 대하여 논의하였다.

• 전기학회논문지
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• 제60권5호
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• pp.1036-1042
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• 2011

This paper presents an algorithm that conducts automatic memory scrubbing operated by dedicated hardwares. The proposed algorithm is designed so that it can scrub entire memory in a given scrub period, while minimally affecting the execution of flight softwares. The scrub controller is constructed in a form of state machines, which have two execution modes - normal mode and burst mode. The deadline event generator and period tick generator are designed in a separate way to support the behavior of the scrub controller. The proposed controller is implemented in VHDL code to validate its applicability. A simple version of the controller is also applied to mass memory modules used in STSAT-3.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권5호
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• pp.445-454
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• 2015

As the feature sizes and the operating charges continue to be scaled down, multi-bit soft errors are becoming more critical in SRAM designs of a few nanometers. In this paper, we propose an efficient error detection technique to reduce the size of parity bits by applying a 2D bit-interleaving technique to 3D bit-partitioned SRAM devices. Our proposed bit-interleaving technique uses only 1/K (where K is the number of dies) parity bits, compared with conventional bit-interleaving structures. Our simulation results show that 1/K parity bits are needed with only a 0.024-0.036% detection error increased over that of the existing bit-interleaving method. It is also possible for our technique to improve the burst error coverage, by adding more parity bits.