• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2126-2130
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• 2003

In the integrated systems, that is integrated digital TV(DTV) internet and home automation, like home server, is needed integration of digital TV video signal and computer graphic signal. The graphic signal is operating at the high speed and has time-divide-stream. So the re-request of data is not easy at the time of error detection. therefore EDAC algorithm is efficient. In this paper, we show a scheme, that is integration of graphic and dtv format signal for DTV monitor display. This paper also presents the efficiency error detection auto correction(EDAC) for conversion of graphics signal to DTV video signal. A presented EDAC algorithms use the modified hamming code for enhancing video quality and reliability. A EDAC algorithm of this paper can detect single error, double error, triple error and more error for preventing from incorrect correction. And it is not necessary an additional memory. In this paper The comparison between digital TV video signal and graphic signal, a EDAC algorithm and a design of conversion graphic signal to DTV signal with EDAC function in DTV system is described.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.106-109
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• 2002

In the integrated systems, that is integrated digital TV(DTV) internet and home automation, like home server, is needed integration of digital TV video signal and computer graphic signal. The graphic signal is operating at the high speed and has time-divide-stream. So the re-request of data is not easy at the time of error detection. therefore EDAC algorithm is efficient. This paper presents the efficiency error detection auto correction(EDAC) for conversion of graphics signal to DTV video signal. A presented EDAC algorithms use the modified Hamming code for enhancing video quality and reliability. A EDAC algorithm of this paper can detect single error, double error, triple error and more error for preventing from incorrect correction. And it is not necessary an additional memory. In this paper The comparison between digital TV video signal and graphic signal, a EBAC algorithm and a design of conversion graphic signal to DTV signal with EDAC function is described.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.417-422
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• 2010

When memory devices are exposed to space environments, they suffer various effects such as SEU(Single Event Upset). Memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, several error detection and correction codes - RS(10,8) code, (7,4) Hamming code and (16,8) code - are analyzed and compared with each other. Each code is implemented using VHDL and its performances(encoding/decoding speed, required memory size) are compared. Also the failure probability equation of each EDAC code is derived, and the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. Finally, the EDAC algorithm for STSAT-3 is determined based on the comparison results.

• Journal of The Korea Institute of Healthcare Architecture
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• v.25 no.1
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• pp.61-66
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• 2019

• Journal of Astronomy and Space Sciences
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• v.22 no.4
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• pp.537-558
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• 2005

This paper addresses the results of HAUSAT-2 radiation environment and effect analyses, including TID and SEE analyses. Trapped proton and electron, solar proton, galactic cosmic ray models were considered for HAUSAT-2 TID radiation environment analysis. TID was analyzed through total dose-depth curve and the radiation tolerance of TID for HAUSAT-2 components was verified by using DMBP method and sectoring analysis. HAUSAT-2 LET spectrum for heavy ion and proton were also analyzed for SEE investigation. SEE(SEU, SEL) analyses were accomplished for MPC860T2B microprocessor and K6X8008T2B memory. It was estimated that several SEUs may occur without SEL during the HAUSAT-2 mission life(2 years). Software Hamming Code EDAC has been implemented to detect and correct the SEU. In this study, all radiation analyses were conducted by using SPENVIS software.

• Tuberculosis and Respiratory Diseases
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• v.78 no.4
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• pp.455-458
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• 2015

Excessive dynamic airway collapse (EDAC) is a disease entity of excessive reduction of the central airway diameter during exhalation, without cartilage collapse. An 80-year-old female presented with generalized edema and dyspnea at our hospital. The patient was in a state of acute decompensated heart failure due to pneumonia with respiratory failure. We accordingly managed the patient with renal replacement therapy, mechanical ventilation and antibiotics. Bronchoscopy confirmed the diagnosis of EDAC. We scheduled extubation after the improvement of pneumonia and heart condition. However, extubation failure occurred due to hypercapnic respiratory failure with poor expectoration. Her EDAC was improved in response to high flow nasal oxygen therapy (HFNOT). Subsequently, the patient was stabilized and transferred to the general ward. HFNOT, which generates physiologic positive end expiratory pressure (PEEP) effects, could be an alternative and effective management of EDAC. Further research and clinical trials are needed to demonstrate the therapeutic effect of HFNOT on EDAC.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.2
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• pp.228-233
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• 2000

It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.

• Aerospace Engineering and Technology
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• v.2 no.1
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• pp.73-79
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• 2003

Usual satellite design adopts hardware Error Detection and Correction (EDAC) circuitary for memory elements to endure proper operation in space radiation environment and periodic read-back(scrubbing) scheme to remove errors occurred and to prevent further accumulation of errors, in parallel, But lack of detail radiation test data upset rates of KOMPSAT-2 mass storage was estimated very worse compared to that of KOMPSAT-1, which was evaluated from very precise radiation test. Although upset rates were evaluated enough low to accommodate by KOMPSAT-2 Flight Software, hardware scrubbing scheme is studied to shorten scrubbing time as well. This paper describes hardware scrubbing architecture having minimum 1.88 minutes scrubbing interval over 1 Gbits memory.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.5
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• pp.1036-1042
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• 2011

This paper presents an algorithm that conducts automatic memory scrubbing operated by dedicated hardwares. The proposed algorithm is designed so that it can scrub entire memory in a given scrub period, while minimally affecting the execution of flight softwares. The scrub controller is constructed in a form of state machines, which have two execution modes - normal mode and burst mode. The deadline event generator and period tick generator are designed in a separate way to support the behavior of the scrub controller. The proposed controller is implemented in VHDL code to validate its applicability. A simple version of the controller is also applied to mass memory modules used in STSAT-3.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.445-454
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• 2015

As the feature sizes and the operating charges continue to be scaled down, multi-bit soft errors are becoming more critical in SRAM designs of a few nanometers. In this paper, we propose an efficient error detection technique to reduce the size of parity bits by applying a 2D bit-interleaving technique to 3D bit-partitioned SRAM devices. Our proposed bit-interleaving technique uses only 1/K (where K is the number of dies) parity bits, compared with conventional bit-interleaving structures. Our simulation results show that 1/K parity bits are needed with only a 0.024-0.036% detection error increased over that of the existing bit-interleaving method. It is also possible for our technique to improve the burst error coverage, by adding more parity bits.