• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.2
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• pp.159-164
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• 2016

A wireless communication system is required to be implemented with the low power circuits because it uses a battery having a limited energy. Therefore, the current mode circuit has been studied because it consumes constant power regardless of the frequency change. However, the clock-feedthrough problem is happened by leak of stored energy in memory operation. In this paper, we suggest the current memory circuit to minimize the clock-feedthrough problem and introduce a technique for ultra low power operation by inducing dynamic voltage scaling. The current memory circuit was designed with BSIM3 model of $0.35{\mu}m$ process and was operated in the near-threshold region. From the simulation result, the clock-feedthrough could be minimized when designing the memory MOS Width of $2{\mu}m$, the switch MOS Width of $0.3{\mu}m$ and dummy MOS Width of $13{\mu}m$ in 1MHz switching operation. The power consumption was calculated with $3.7{\mu}W$ at the supply voltage of 1.2 V, near-threshold voltage.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.4
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• pp.857-866
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• 2009

In this paper, a noise cancellation-method using microphone array for digital hearing aids is proposed. The microphone array is located around the ear of a dummy. Speech sound is generated from the forward speaker positioned in the front of the dummy and noise sound is generated from the backward speaker. The speech and noise are mixed in the air space and entered into the microphones. VAD(voice activity detector) and ANC(adaptive noise cancellation) methods were used to eliminate noise in the sound of the microphones. 10 two-syllable words and 4 sentences were used for speech signals. Babble and car interior noise were used for noise signals. The performance of the proposed algorithm was evaluated by SNR(signal-to-noise ratio) and PESQ-MOS(perceptual evaluation of speech quality-mean opinion score). In babble noise condition, SNR was improved as much as $7.963{\pm}1.3620dB\;and\;3.968{\pm}0.6659dB$ for words and sentences respectively. In the case of car interior noise, SNR was improved as $10.512{\pm}2.0665dB\;and\;6.000{\pm}1.7642dB$ for words and sentences respectively. PESQ-MOS of the babble noise was improved as much as $0.1722{\pm}0.0861$ score for words and $0.083{\pm}0.0417$ score for sentences. And PESQ-MOS of the car interior noise was improved as $0.2661{\pm}0.0335$ score and $0.040{\pm}0.0201$ score for words and sentences respectively. It is verified that the proposed algorithm has a good performance in noise cancellation of microphone array for digital hearing aids.

• ETRI Journal
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• v.30 no.6
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• pp.826-832
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• 2008

The metal-ferroelectric-metal (MFM) capacitor in the ferroelectric random access memory (FeRAM) embedded RFID chip is used in both the memory cell region and the peripheral analog and digital circuit area for capacitance parameter control. The capacitance value of the MFM capacitor is about 30 times larger than that of conventional capacitors, such as the poly-insulator-poly (PIP) capacitor and the metal-insulator-metal (MIM) capacitor. An MFM capacitor directly stacked over the analog and memory circuit region can share the layout area with the circuit region; thus, the chip size can be reduced by about 60%. The energy transformation efficiency using the MFM scheme is higher than that of the PIP scheme in RFID chips. The radio frequency operational signal properties using circuits with MFM capacitors are almost the same as or better than with PIP, MIM, and MOS capacitors. For the default value specification requirement, the default set cell is designed with an additional dummy cell.