• Title/Summary/Keyword: Driving Signal

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An Area-Efficient Time-Shared 10b DAC for AMOLED Column Driver IC Applications (AMOLED 컬럼 구동회로 응용을 위한 시분할 기법 기반의 면적 효율적인 10b DAC)

  • Kim, Won-Kang;An, Tai-Ji;Lee, Seung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.5
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    • pp.87-97
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    • 2016
  • This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

A l0b 150 MSample/s 1.8V 123 mW CMOS A/D Converter (l0b 150 MSample/s 1.8V 123 mW CMOS 파이프라인 A/D 변환기)

  • Kim Se-Won;Park Jong-Bum;Lee Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.1
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    • pp.53-60
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    • 2004
  • This work describes a l0b 150 MSample/s CMOS pipelined A/D converter (ADC) based on advanced bootsuapping techniques for higher input bandwidth than a sampling rate. The proposed ADC adopts a typical multi-step pipelined architecture, employs the merged-capacitor switching technique which improves sampling rate and resolution reducing by $50\%$ the number of unit capacitors used in the multiplying digital-to-analog converter. On-chip current and voltage references for high-speed driving capability of R & C loads and on-chip decimator circuits for high-speed testability are implemented with on-chip decoupling capacitors. The proposed AU is fabricated in a 0.18 um 1P6M CMOS technology. The measured differential and integral nonlinearities are within $-0.56{\~}+0.69$ LSB and $-1.50{\~}+0.68$ LSB, respectively. The prototype ADC shows the signal-to-noise-and-distortion ratio (SNDR) of 52 dB at 150 MSample/s. The active chip area is 2.2 mm2 (= 1.4 mm ${\times}$ 1.6 mm) and the chip consumes 123 mW at 150 MSample/s.

A 0.16㎟ 12b 30MS/s 0.18um CMOS SAR ADC Based on Low-Power Composite Switching (저전력 복합 스위칭 기반의 0.16㎟ 12b 30MS/s 0.18um CMOS SAR ADC)

  • Shin, Hee-Wook;Jeong, Jong-Min;An, Tai-Ji;Park, Jun-Sang;Lee, Seung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.7
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    • pp.27-38
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    • 2016
  • This work proposes a 12b 30MS/s 0.18um CMOS SAR ADC based on low-power composite switching with an active die area of $0.16mm^2$. The proposed composite switching employs the conventional $V_{CM}$-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. Two equally-divided capacitors topology and the reference scaling are employed to implement the $V_{CM}$-based switching effectively and match an input signal range with a reference voltage range in the proposed C-R hybrid DAC. The techniques also simplify the overall circuits and reduce the total number of unit capacitors up to 64 in the fully differential version of the prototype 12b ADC. Meanwhile, the SAR logic block of the proposed SAR ADC employs a simple latch-type register rather than a D flip-flop-based register not only to improve the speed and stability of the SAR operation but also to reduce the area and power consumption by driving reference switches in the DAC directly without any decoder. The measured DNL and INL of the prototype ADC in a 0.18um CMOS are within 0.85LSB and 2.53LSB, respectively. The ADC shows a maximum SNDR of a 59.33dB and a maximum SFDR of 69.83dB at 30MS/s. The ADC consumes 2.25mW at a 1.8V supply voltage.

Seismic AVO Analysis, AVO Modeling, AVO Inversion for understanding the gas-hydrate structure (가스 하이드레이트 부존층의 구조파악을 위한 탄성파 AVO 분석 AVO모델링, AVO역산)

  • Kim Gun-Duk;Chung Bu-Heung
    • 한국신재생에너지학회:학술대회논문집
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    • 2005.06a
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    • pp.643-646
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    • 2005
  • The gas hydrate exploration using seismic reflection data, the detection of BSR(Bottom Simulating Reflector) on the seismic section is the most important work flow because the BSR have been interpreted as being formed at the base of a gas hydrate zone. Usually, BSR has some dominant qualitative characteristics on seismic section i.e. Wavelet phase reversal compare to sea bottom signal, Parallel layer with sea bottom, Strong amplitude, Masking phenomenon above the BSR, Cross bedding with other geological layer. Even though a BSR can be selected on seismic section with these guidance, it is not enough to conform as being true BSR. Some other available methods for verifying the BSR with reliable analysis quantitatively i.e. Interval velocity analysis, AVO(Amplitude Variation with Offset)analysis etc. Usually, AVO analysis can be divided by three main parts. The first part is AVO analysis, the second is AVO modeling and the last is AVO inversion. AVO analysis is unique method for detecting the free gas zone on seismic section directly. Therefore it can be a kind of useful analysis method for discriminating true BSR, which might arise from an Possion ratio contrast between high velocity layer, partially hydrated sediment and low velocity layer, water saturated gas sediment. During the AVO interpretation, as the AVO response can be changed depend upon the water saturation ratio, it is confused to discriminate the AVO response of gas layer from dry layer. In that case, the AVO modeling is necessary to generate synthetic seismogram comparing with real data. It can be available to make conclusions from correspondence or lack of correspondence between the two seismograms. AVO inversion process is the method for driving a geological model by iterative operation that the result ing synthetic seismogram matches to real data seismogram wi thin some tolerance level. AVO inversion is a topic of current research and for now there is no general consensus on how the process should be done or even whether is valid for standard seismic data. Unfortunately, there are no well log data acquired from gas hydrate exploration area in Korea. Instead of that data, well log data and seismic data acquired from gas sand area located nearby the gas hydrate exploration area is used to AVO analysis, As the results of AVO modeling, type III AVO anomaly confirmed on the gas sand layer. The Castagna's equation constant value for estimating the S-wave velocity are evaluated as A=0.86190, B=-3845.14431 respectively and water saturation ratio is $50\%$. To calculate the reflection coefficient of synthetic seismogram, the Zoeppritz equation is used. For AVO inversion process, the dataset provided by Hampson-Rushell CO. is used.

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Design of a Highly Integrated Palette-type High Power Amplifier Module Using GaN Devices for DPD Application (질화갈륨 소자를 이용한 DPD용 고집적 팔렛트형 고출력증폭기 모듈 설계)

  • Oh, Seong-Min;Lim, Jong-Sik
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.12 no.5
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    • pp.2241-2248
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    • 2011
  • This paper describes the design of a palette-type 60watt high power amplifier module using gallium nitride(GaN) devices with high power and efficiency performances for WiMAX and LTE systems. The line-up for the high gain amplifier module consists of the pre-amplifier stage with low power and high gain, 8watt GaN driving amplifier stage, and 60watt GaN high power amplifier stage of Doherty structure with two 30watt GaN devices. The obtained gain is 61.4dB with an excellent gain flatness of ${\pm}$0.075dB over 2.5~2.68GHz. GaN devices and the Doherty structure are adopted for the improvement of high efficiency and output power. The measurement for the fabricated high power amplifier module of palette type is performed using the widely known WiMAX signal all over the world. In the example of RRH(remote radio head) application of the fabricated amplifier module, the measured efficiency is 37~38% with the 10watts of modulated output power. It is shown that when the fabricated amplifier module is activated with a digital predistorter(DPD), the measured ACLR is better than 46dBc under the 10watts of modulated output power.

Magnitudes of the Harmonic Components Emitted from Utrasonic Contrast Agents in Response to a Diagnostic Utrasound: Theoretical Consideration (진단용 초음파에 의해 가진된 초음파 조영제에서 방사하는 하모닉 성분의 크기: 이론적 고찰)

  • Kang Gwan Suk;Yu Ji Chul;Paeng Dong Guk;Rhim Sung Min;Choi Min Joo
    • The Journal of the Acoustical Society of Korea
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    • v.24 no.2
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    • pp.78-86
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    • 2005
  • This study considers the magnitude of the harmonic components radiated from the ultrasonic contrast agents (UCA) activated by a typical diagnostic ultrasound. The nonlinear dynamic response of UCA to a 2 MHz diagnostic ultrasound pulse was predicted using Gilmore Model. The elastic property of the shell membrane of the UCA was ignored in the numerical model. Simulation was carried out for the UCA varying from 1 - 9 $\mu$m in its initial radius and the driving diagnostic ultrasound whose mechanical index (MI) ranges from 0.125 to 8. The powers of the sub. ultra and second harmonics of the acoustic signal from the UCA activated were compared with that of the fundamental component. The results show that. if the UCA is bigger than its resonant size (2 $\mu$m in radius for the present case) the sub harmonic power was much bigger than the fundamental. In particular, the 2nd harmonic component currently used as an imaging parameter for the harmonic imaging, was predicted to be lower in power than both the sub and the ultra harmonic component. This study indicates that, for obtaining harmonic imaging with UCA, the sub or ultra harmonics could be taken as imaging parameters better than the 2nd harmonic component.

Development of Digital Image Acquisition System for the Road Safety Survey and Analysis Vehicle (도로안전성 조사분석차량을 위한 영상취득시스템 개발)

  • Jeong, Dong-Hoon;Yoon, Chun-Joo;Sung, Jung-Gon
    • International Journal of Highway Engineering
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    • v.7 no.4 s.26
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    • pp.163-171
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    • 2005
  • Current roads were designed and constructed based on the design criteria and thus those were overly simplified drivers' needs. The road criteria do not suggest the desirable range of the design values but suggest the minimum requirements for the road design. Therefore, a completed road design based on the design criteria does not always guarantee the best design in terms of safety and it sometimes violates drivers' expectation. Therefore, the ROSSAV(ROad Safety Survey and Analysis Vehicle) is being developed by the KICT to evaluate road safety and increase driving safety. In this paper, the image capture system was described in detail. The image capture system is consisted of two front view cameras, two side down-looking cameras and a synchronization device. Two front view cameras were used to take a picture of road and road facilities at the driver's viewpoint. Also, two side down-looking cameras were used to capture road surface image to extract lane markings. A synchronization device were used to generate image capturing signal at the fixed distance spacing huck as every 10m. The front view images could be used to calculate and measure highway geometry such as shoulder width because every image is saved with it's locational information. And also the side down looking images could be used to extract median lane mark which representing road alignement efficiently.

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Characteristics of Beam-tilting Slot Array Waveguide Antennas for DBS Reception (DBS 수신용 빔 틸트형 슬롯 어레이 도파관 안테나의 특성)

  • Min, Gyeong-Sik;Kim, Dong-Cheol;Arai, Hiroyuki
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.39 no.3
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    • pp.140-149
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    • 2002
  • This paper describes the characteristics of beam-tilting slot away waveguide antennas for mobile DBS reception. As a basic study of slotted waveguide array, design for 16 slot elements located on a broad-wall waveguide is considered. Design parameters such as slot length, space between each slot and cross slot angle of antennas with the beam-tilting characteristics are calculated by method of moments. Based on these results, the radiation waveguide antennas with 16-element $\times$16-array are designed and fabricated. The measured main beam direction angles of the fabricated antennas are 48$^{\circ}$to 50$^{\circ}$depending on the measured frequencies and it shows good agreement with prediction. The measured 3 dB beam width of elevation pattern is about 13$^{\circ}$, and the axial ratio and the gain measured at DBS band are observed 2.8 dB below and 24 dBi above, respectively. In order to evaluate a performance of the fabricated waveguide planar antenna, it is combined with the satellite tracking control system and the field performance test of antenna mounted on a mobile vehicle is carried out at highway. During the measurement, it was possible to watch television without a break signal in a driving vehicle and an excellent performance of the proposed antennas was demonstrated.

A New Structural Carry-out Circuit in Full Adder (새로운 구조의 전가산기 캐리 출력 생성회로)

  • Kim, Young-Woon;Seo, Hae-Jun;Han, Se-Hwan;Cho, Tae-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.12
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    • pp.1-9
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    • 2009
  • A full adders is an important component in applications of digital signal processors and microprocessors. Thus it is imperative to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional static CMOS and pass transistor logic. The carry-out generation circuit of the proposed full adder is different from the conventional XOR-XNOR structure. The output Cout of module III is generated from input A, B and Cin directly without passing through module I as in conventional structure. Thus output Cout is faster by reducing operation step. The proposed module III uses the static CMOS logic style, which results full-swing operation and good driving capability. The proposed 1bit full adder has the advantages over the conventional static CMOS, CPL, TGA, TFA, HPSC, 14T, and TSAC logic. The delay time is improved by 4.3% comparing to the best value known. PDP(power delay product) is improved by 9.8% comparing to the best value. Simulation has been carried out using a $0.18{\mu}m$ CMOS design rule for simulation purposes. The physical design has been verified using HSPICE.

Development of Liquid Crystal Optic Modulation Based X-ray Dosimeter by Using CdS Sensor (CdS 센서를 이용한 액정 광변조 X-선 검출 시스템 개발)

  • Noh, Si-Cheol;Kang, Sang-Sik;Jung, Bong-Jae;Choi, Il-Hong;Kim, Hyun-Hee;Cho, Chang-Hoon;Park, Jun-Hong;Park, Ji-Koon
    • Journal of the Korean Society of Radiology
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    • v.5 no.6
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    • pp.357-361
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    • 2011
  • In this study, the liquid-crystal optical modulation X-ray detection system using a CdS which is a family of II-IV compound semiconductor was proposed. The system consist of the detector, the signal processing part, the liquid-crystal driving parts, microcontroller, and I/O parts, and was designed to be suitable for miniaturization and portable. In addition, the system can measure a wide range X-ray by using the detecting range selection. In order to evaluate the performance of the proposed system, the CdS sensor's output characteristics were confirmed in accordance with changes of dose, and excellent correlation was determined. And also, the optical penetration ratio was discussed in accordance with changes of the applied voltage by measuring the change of the liquid-crystal in accordance with changes of the applied voltage. Through these results, the characteristics of the liquid-crystal optical modulation system such as the excellent reproducibility and the noise immunity were confirmed. And we considered that the CdS cell-based liquid-crystal optical modulated portable X-ray detection system could be applied to compact, low-cost, portable system.